category: Top Stories

category: Auto, Security & Edge AI

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Inside FD-SOI And Scaling
By Mark LaPedus - 15 Jun, 2017 - Comments: 5

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

Modeling On-Chip Variation At 10/7nm
By Ann Mutschler - 14 Jun, 2017 - Comments: 1

Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

2.5D, ASICs Extend to 7nm
By Mark LaPedus - 13 Jun, 2017 - Comments: 2

The leading-edge foundry market is heating up. For example, GlobalFoundries, Intel, Samsung and TSMC have recently announced their new and respective processes. The new processes from vendors range anywhere from 10nm to 4nm, although the current battle is taking place at 10nm and/or 7nm. In fact, one vendor, GlobalFoundries, this week will describe more details about its previously-announced... » read more

The LiDAR Gold Rush
By Jeff Dorsch - 12 Jun, 2017 - Comments: 0

Big money is pouring into the LiDAR market, as carmakers gear up for autonomous and assisted driving. LiDAR, along with advanced computer vision and radar sensors, is an essential component for vehicles to maneuver without hitting obstacles or other cars. LiDAR is an acronym for light imaging, detection, and ranging, and until now it has been almost synonymous with next-generation automotive... » read more

Transient Power Problems Rising
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

Safety Plus Security: A New Challenge
By Brian Bailey - 08 Jun, 2017 - Comments: 0

Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Hardware/Software Tipping Point
By Brian Bailey - 08 Jun, 2017 - Comments: 0

It doesn't matter if you believe [getkc id="74" comment="Moore's Law"] has ended or is just slowing down. It is becoming very clear that design in the future will be significant different than it is today. Moore's law allowed the semiconductor industry to reuse design blocks from previous designs, and these were helped along by a new technology node—even if it was a sub-optimal solution. I... » read more

Chip Test Shifts Left
By Jeff Dorsch - 07 Jun, 2017 - Comments: 0

“Shift left” is a term traditionally applied to software testing, meaning to take action earlier in the V-shaped time line of a project. It has recently been touted in electronic design automation and IC design, verification, and test. “Test early and test often” is the classic maxim of software testing. What if that concept could also be implemented in semiconductor testing, to redu... » read more

Security Issues Up With Heterogeneity
By Ann Mutschler - 05 Jun, 2017 - Comments: 0

The race toward heterogeneous designs is raising new security concerns across the semiconductor supply chain. There is more IP to track, more potential for unexpected interactions, and many more ways to steal data or IP. Security is a difficult problem no matter what kind of chip is involved, and it has been getting worse as more devices, machines and systems are connected to the Internet. B... » read more

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