Executive Insight: Hossein Yassaie


SE: What concerns you looking out at the semiconductor industry? Yassaie: There are big changes in the industry over the last two years, such as the verticalization in the mobile space. Every semiconductor company wanted to play in mobile. It was just a fact of life that some of these guys would give up. That was a major change, and it was something we could see coming. Our focus is diverse ... » read more

Executive Insight: Prakash Narain


SE: What’s your biggest concern? Narain: We are a smaller company, and ultimately we compete on the basis of the quality of the solutions we provide to customers. What’s the value proposition? How many X better will our solution be compared to the existing solutions that are in deployed in the market? You make a projection about it in your mind, and you make investments, and until they�... » read more

Test Challenges Grow


Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our ... » read more

Self-Service Comparisons Come To SoC Design


Under the guise of enabling self-service comparison of its compilable memories and providing self-service online quoting of TSMC technology, semiconductor design and manufacturing services provider eSilicon Corp. detailed the latest evolution of its business model—and one that could have interesting implications for the IP and memory markets. This move reflects the changing dynamics of cus... » read more

New Business Model: Flexible Silos


Operational silos within organizations have a long history of streamlining processes and maximize efficiency. In fact, that approach has made enterprise resource planning applications a must-have for most companies, and cemented the fortunes of giants such as SAP and Oracle, as well as the giant consulting companies that recommend them. But those kinds of delineations don’t work so well fo... » read more

The Assertion Conundrum


It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous. Part of the reason is that assertions cannot be picked up casually, noted David Larson, director of verification at [getentity id="22150" e_name="Synapse Design"]. “This is because asserti... » read more

New Uses For Emulation


Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

When And Where To Use Virtual Prototypes


Just because something is technically possible doesn’t always mean it should be done. This definitely holds true currently when it comes to virtual prototypes, which have gotten a lot of attention for their potential in the SoC design process—especially for concurrent software development. While no one is pointing fingers, there are situations in which design teams have thrown themselves... » read more

Executive Insight: Adnan Hamid


Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization. ... » read more

Big Memory Shift Ahead


System architecture has been driven by the performance of [getkc id="22" kc_name="memory"]. Processor designers would have liked all of the memory be fast [getkc id="92" kc_name="SRAM"], placed on-chip for maximum performance, but that was not an option. Memory had to be fabricated as separate chips and connected via a Printed Circuit Board (PCB). That limited the number of available I/O ports ... » read more

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