category: Top Stories

category: Auto, Security & Edge AI

Cracking The Tough Nut Using Formal Methods
By Brian Bailey - 21 Nov, 2013 - Comments: 1

Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Phosphors Turn Blue LED Lights White
By Katherine Derbyshire - 18 Nov, 2013 - Comments: 0

LEDs inherently produce monochromatic light. An excited electron decays back to the ground state, releasing its energy in the form of a photon. The wavelength of this photon is defined by the band structure of the semiconductors used to make the LED. While monochromatic light is fine for indicator lights, most display and general lighting applications use white light. Not only is white light... » read more

Experts At The Table: What’s Missing In The IoT
By Ed Sperling - 15 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of the IoT with Oleg Logvinov, director of market development for STMicroelectronics’ Industrial and Power Conversion Division; Martin Lund, senior vice president of the IP Group at Cadence; Naveed Sherwani, president and CEO of Open-Silicon; and Damon Hernandez, a member of the Web3D Consortium. What follows are excerpts of that conver... » read more

From DFM To IFM
By Ed Sperling - 14 Nov, 2013 - Comments: 0

For the past decade the bridge between design and manufacturing was called, appropriately enough, design for manufacturing. DFM tools, which by nature cross boundaries of what previously were discrete segments in the semiconductor flow, are now critical for complex designs. They allow design teams to check early in the design process whether chips will yield sufficiently and to incorporate rule... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

Collaborate Or Go Home
By Jeff Chappell - 14 Nov, 2013 - Comments: 0

Technology is hard. It's no secret that it's more difficult than ever to keep devices shrinking while increasing performance. It's also old news that it is increasingly costly to be at the leading edge, as semiconductor production technology gets ever more complex — even as a maturing chip industry becomes ever more dependent on low-cost consumer devices. But it has made for some strang... » read more

Tunnel FETs Emerge In Scaling Race
By Mark LaPedus - 14 Nov, 2013 - Comments: 2

Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers. In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate... » read more

What’s After 10nm?
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions. Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based ... » read more

Momentum Builds For Monolithic 3D ICs
By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

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