Targeted design for test, better fault models, and in-system testing must keep pace with advanced-node components.
The automotive industry is producing vehicles with increasing levels of real-time decision-making, enabled by thousands of ICs, sensors, and multi-chip packages, but making sure these systems work flawlessly throughout their expected lifetimes is a growing challenge.
Automotive chips traditionally were developed at mature process nodes in five- to seven-year cycles, but much has changed over the past half-decade. Mechanical systems have been replaced with advanced driver assistance systems (ADAS), complex infotainment, and chiplet-based systems that rely on high-performance computing to process more sensor data in real-time.
Attaining automotive grade quality levels (<1 defective part per million, DPPM) over the wide range of power devices, flash memories, display drivers, and electronic control units is a daunting task. It requires substantial innovation from the design-for-test and test community.
“The greatest challenge is the quality requirement derived from safety standards, which means aiming for ‘zero DPPM,’” said Nir Sever, senior director of business development at proteanTecs. “No other industry requires such a quality level for such complex devices and at scale. In addition, the requirement for extended lifetime, far beyond that of other commercial devices, puts more need for margins that, again, challenge testing methods.”
In addition to the zero-DPPM goal, there is constant pressure to keep test costs low to enable chipmakers to maintain sufficient gross margins. The delicate balance between quality/test coverage and cost is becoming harder to manage in the face of manufacturing leading-node chips, modules, and systems.
Progress in advanced driver assistance
“ADAS really started the trend in automotive of targeting the more advanced, smaller nodes,” said Lee Harrison, director of automotive test solutions at Siemens EDA. “However, this application has expanded from just ADAS to full software-defined vehicles (SDVs), where the central compute hardware manages more than just the ADAS. It also manages many functions within the car, from heated seats to windscreen wipers to autonomous driving capabilities.”
The rate of change in automotive is accelerating. “In the past, automotive chips were based on mature technology node devices and the design was hardware-centric,” said Fisher Zhang, general manager of the Complex SoC Business Unit at Teradyne. “But in the last few years, technology adoption has accelerated with increasing autonomy, electric vehicle (EV) adoption, and an increasing number of semiconductor devices per car. Ensuring the highest quality at a reasonable test cost is the greatest challenge.”
For some vehicles, these changes include round-the-clock use, which is compounded by the push to next-node processes. “Carmakers are pushing for sub-5nm designs to enhance performance, which introduces challenges in reliability and safety,” said Jyotika Athavale, director of engineering architecture at Synopsys, pointing to new use cases that alter the mission profile and impact reliability testing. “The move toward ‘always-on’ models, such as robotaxis, requires silicon to operate for up to 130,000 hours over 15 years compared to the traditional 8,000 hours.”
Advanced-node chips provide increased processing density, which improves reaction time, and lower power consumption, which in EVs translates into increased range. But they also make testing more challenging, particularly when it involves multi-die assemblies with chiplets.
“ADAS devices are following the HPC device trend, moving to smaller process nodes to increase computing power while keeping power dissipation at moderate levels,” said Toni Dirscherl, business team lead for V93000 Power/Analog/Control at Advantest. Such high-performance compute testing requires high-speed interfaces on the tester to rapidly transfer test content. “For ADAS chips we are getting requests for concurrent test of individual chiplets and test bus access via high-speed I/O.”
For ADAS SoCs, systematic methods for built-in self-test (BiST) apply at shipment and during field use. “Adaptive test strategies using high-speed access test enable per-die calibration and high fault coverage for performance-sensitive logic,” said Pawini Mahajan, senior staff product manager at Synopsys. “In-system observability using the Star memory system (memory BiST) enables proactive reliability validation during field operation.”
ADAS levels 2 – 5
ADAS has five levels of implementation. Today, most new vehicles are at L2 or L3 (see figure 1). “As we move to higher levels of ADAS, more of the ADAS components will be required to meet a higher safety standard as you take more and more of the human out of the loop,” said Siemens EDA’s Harrison. “Developing large systems to meet ISO 26262 ASIL-D is a significant challenge.”
Fig. 1: Levels of ADAS. Source: SAE
ISO26262 defines four Automotive Safety Integrity Levels, ISIL A through D. ASIL A addresses the lowest degree of automotive hazard, while ASIL D addresses the highest degree of safety integrity, which includes power steering, airbags, and anti-lock brakes. In addition, ADAS defines five levels of automation. Most vehicles today are at L2 (partial driving automation) or L3 (conditional driving automation, some eyes off). L5 is fully autonomous.
At L3, vehicles are outfitted with thousands of sensors, including radar, cameras, lidar, ultrasonic sensors, and more. Deployment of these sensors generates massive amounts of data, which needs to be processed in real-time to trigger immediate reactions. “A large number of sensor signals have to be processed, requiring data fusion, and algorithms have to run and reach decisions at the same time as controller activation,” said Roland Janke, head of department design methodology at Fraunhofer IIS’ Engineering of Adaptive Systems Division.
Because the transition from L3 to L4 is such a big technological leap, experts say another transitional level is likely. “After [L3], instead of going to L4 development, it will continue with intermediate levels like 3+,” said Janke. “For higher levels of automation, it no longer will be possible to test all functionality in a real car on the road. Instead, the percentage of virtual tests will significantly increase.”
Virtual testing is essentially a digital twin version of the testing process. “It is done by providing a virtual prototype of the hardware and test, either as a reduced version of the software that concentrates on specific topics like functionality or timing, or even the full software on that virtual prototype,” explains Janke. “Virtual testing will become significantly more important in order to reduce real tests on the road for complex hardware/software systems. An important advantage of virtual hardware is that it allows software to be developed and tested even before the physical hardware is available, thereby parallelizing both developments and saving time to market.”
Janke notes that while extra work is required to build such respective models, there are advantages such as reuse in communications with suppliers. Those models also could serve as golden references for the hardware implementation.
What goes into automotive testing
Automotive is a safety-critical application for semiconductors, making quality the highest concern because lives are at stake. One of the key ways automotive integrated circuits are treated differently on the test floor is that they are stress tested at three temperatures (-40°C/105°C/175°C) to effectively mimic the operating temperatures they need to endure. Those three temperatures depend on the automotive grade as defined by another standard, AEC-Q100. Automotive chips also undergo high temperature operating lifetime (HTOL) testing and package-level burn-in prior to the final test step.
Automotive IC customers demand higher test coverage and often use machine learning-based outlier detection methods to drive quality levels to the near-zero DPPM level. In addition to high quality, binning is a common practice in automotive.
“Our technology enables process grading at the individual chip level, allowing customers to perform real-time binning directly on the tester, starting at day zero,” said Eidan Mendelsohn, director of data engineering and data analytics at proteanTecs. “Additionally, we provide advanced machine learning tools that leverage the chip’s unique process signature to build predictive models. These models are used to reduce DPPM, shorten test time, and improve overall yield and cost through shift-left strategies. At advanced process nodes, where variability and defect sensitivity are significantly higher, this level of insight becomes even more critical.”
The number of semiconductor components in automobiles has soared from the modest level of several hundred in cars with internal combustion engines to as many as 5,000 in electric vehicles. “With a larger number of chips, you still want to maintain the same quality, the same low defect level as a whole,” said Teradyne’s Zhang. “So the quality requirement of each component is actually going up.”
Pawini Mahajan, senior staff product manager at Synopsys detailed the challenges in automotive testing:
Fault models always are improving and new models are coming online. “Advanced fault models, over and above the regular stuck-at and transition fault models, are able to more accurately model common defects found in silicon to create targeted patterns for these different defects, such as physical bridging/opens/cell neighborhood faults,” said Siemens EDA’s Harrison. “We are even looking at stress test fault models to stress the transistors at manufacture, helping to identify any hidden latent faults which could result in early life failure of the silicon.”
Other challenges are specific to the tests and the testing itself. “In three-temperature testing, keeping the die temperature in the expected temperature range while testing is a challenge. And the device under test board space (load board and probe card complexity) is limiting the maximum parallel test capabilities,” said Advantest’s Dirscherl. “Test program development time is long for these huge test programs that have many analog parameters. They require extensive correlation efforts.”
To improve outlier detection, chipmakers are using AI programs and on-chip sensors. “Our Agents serve as an effective indicator of test coverage by revealing which logic cones are being exercised during test execution,” said proteanTecs’ Sever. “To address low DPPM, our analytics software provides a suite of real-time outlier detection methods, including IDDQ-based, margin-based, and VDDmin-based outlier detection. These are accessible at the tester level through a machine-learning-based edge library, enabling real-time quality decisions and outgoing quality improvements.”
In early-stage manufacturing and high-volume production, chipmakers also use several test insertions to reduce early life failures (so-called hard failures), and stress testing (using voltage and/or temperature stress) to drive latent defects (so-called soft failures) to failure.
“The key to automotive is continuous improvement, which means you cannot get the perfect chip from day one, but you enable the process to improve again and again,” said Teradyne’s Zhang. “We have some solutions that allow you, for example, to write your own rules in testing, almost like the design rules. You can minimize the risks, but at the same time learn from the past with the best tools and process behind it.”
Chiplet-based packages
The automotive industry is beginning to adopt chiplet-based designs. The advantages of this approach are clear in the long run. Rather than designing and fabricating all functions in a leading node system-on-chip with a large, reticle-sized die, the constituent parts can be disaggregated into individual chiplets developed at different technology nodes and using smaller die sizes, thereby improving yield and enabling greater reuse and faster time-to-market compared with a planar SoC.
Many testing resources are shifting to the wafer level to guarantee KGD prior to the assembly and packaging of multi-chiplet systems. “You need known-good die,” said Teradyne’s Zhang. “People will be shipping known-good wafers, so you need more and more intensive tests at the wafer stage. As a result, people are shifting test to the left.”
That shift comes at a cost, however. Adding on-die monitors and test structures impact the silicon footprint, engineering hours, and test time. “[Chiplet-based design] implies the need for extra structures and test mode entries on each chiplet, which adds up to significantly more effort in terms of silicon and test time,” said Fraunhofer’s Janke.
The 48V on-board power network includes a key group of devices that should benefit from the modular chiplet approach, according to Janke. These 48V systems feature reduced currents and lower the total copper weight in the vehicle. “This has significant influence on the semiconductor technologies, which need to include power devices capable of handling 48V nominal plus safety headroom. Advanced-node technologies are not known as being ideally suited for these voltages, which is one of the arguments for implementing the chiplet approach.”
Meanwhile, a lack of access to die-die and die-substrate interconnects requires greater reliance on inspection tools capable of seeing below silicon surfaces, such as acoustic and X-ray technologies. Acoustic wafer inspection tools can identify defects in bonds between two wafers in the 10nm range. The acoustic signal sent through a deionized water medium works by detecting minute gaps between the wafers. Bond strength tends to be highest near the wafer center and lower at the wafer edges. A spinning acoustic inspection system can zero-in on these wafer edge voids or defects because the acoustic signal does not travel through air.
Jiangtao Hu, senior director of product management at Onto Innovation, notes that acoustic technology is especially well suited to monitoring interfacial properties in under-bump metal, where tiny voids eventually can precipitate into reliability failures. “These metals are opaque to optical signals, so acoustic is the technology of choice,” said Hu.
Another technology that helps with wafer-wafer bonding characterization is white light interferometry. “The wafer edge roll-off properties, created by the CMP process, tend to influence how well one wafer bonds to another wafer,” said Samuel Lesko, head of applications development at Bruker. “So it’s important to keep track of what the topography looks like. Optical profilers have enough natural resolution and extreme nanometer sensitivity over vertical distances, so the customer takes multiple measurements of the drop-off slope as part of the quality control that precedes wafer bonding.”
Inspection tools generally must deliver higher levels of precision and throughput, despite shrinking feature sizes, even for advanced packaging. “Probably the single biggest challenge facing us really is just keeping up with the node size reduction,” said John Hoffman, computer vision engineering manager at Nordson Test & Measurement. “Pitches are shrinking rapidly. So if the node sizes is being cut in half, for instance, that means my inspection size shrinks by a factor of four, so the inspection takes four times as long, as a rough calculation.”
In-field and in-system testing
“Today, in-field testing for automotive applications primarily supports predictive maintenance, including real-time mission mode testing using embedded sensors and monitors to measure parameters such as path margin or memory timing that indicate device degradation,” said Synopsys’ Athavale. Detecting this degradation prior to failure is critical. “As the industry moves toward autonomous vehicles, in-field testing will evolve to address increased AI workloads that will introduce higher failure rates, necessitating broader and more advanced in-field testing with higher test coverage.”
Fig. 2: Illustration showing on-chip monitors, high-speed I/O interface, test program IP, and failure analysis methodology for in-field debug and diagnosis. Source: Synopsys
In-system testing involves testing the whole system, both hardware and software, to ensure it operates as intended in terms of functional and non-functional requirements. “In-system testing is becoming almost a must-have for automotive silicon,” said Siemens EDA’s Harrison. “This can be covered by a variety of solutions both as in-system structural testing and in-system software testing via software test libraries. Typically the structural in-system testing will give a very high defect coverage, whereas the functional software test libraries are used to target specific functions.”
Fig. 3: Deterministic testing via on-chip streaming scan network test infrastructure. Source: Siemens EDA
“The go-to technology for in-system testing is mainly BiST-based, both MBiST and LBiST,” said Harrison. “As the quality requirements increase, in-system deterministic testing is a technology that can bridge that gap, increasing the quality of test that is achieved with logic BiST to the same level of quality that can be achieved during manufacturing test. Tessent IST, launched back in November 2024, enables the in-system delivery of deterministic test patterns using on-chip embedded software stack. This shifts the typical achievable test coverage in-system with logic BiST from the low 90% to the high 98%-plus.”
Just as there is increasing focus on the automotive system, there is increasing focus on maintaining the test cell. “Focus on complete test cell inter-operation becomes more important,” said Advantest’s Dirscherl. “Issues such as active thermal cooling, individual thermal management per site, and socket/probe contact monitoring for high current paths are important.”
Given the increasing number of contacts on tester sockets and burn-in sockets, the characterization and maintenance of coaxial sockets is gaining attention as well. “We need to measure the contact resistance of the contacts,” said Glenn Cunningham, director of Test and Characterization at Modus Test, in a recent blog. “We also need the ability to measure the effectiveness of the coaxial structures, such as signal and power pin isolation from the Vss shielding block and the Vss pin to the shielding block performance, which all contribute to the coaxial socket’s ability to shield high-speed signals from insertion/return losses, as well as crosstalk. Good contact resistance alone will not guarantee good yield.”
Periodic testing with socket testing protocols in test houses or at OSATs can ensure known good socket use.
How will software-defined vehicles change qualification?
As automobiles become increasingly defined by software, engineers are tracking the software’s effect on actual chip performance. “As software increasingly defines hardware behavior in automotive systems, it’s critical to understand how running the application impacts silicon performance,” said proteanTecs’ Mendelsohn.
Manufacturers must be able to see and track the software effects on the hardware, at time zero and onwards, especially due to over-the-air updates.
“With ML-driven on-chip monitoring, we offer such visibility by correlating test-time reliability predictions with real-time, in-field operational conditions. The agents continue to monitor during the lifetime of the system, to track performance degradations for failure prevention, remote diagnostics, and predictive maintenance,” Mendelsohn explained. “This approach enables precise monitoring of actual versus expected performance. It also allows customers to trace the root cause of any observed performance shifts.”
Conclusion
Because vehicles operate for 12 to 15 years, compared to the typical 3 to 7 years for data centers, for instance, automotive testing must meet much higher reliability and safety standards than the average IC. Continuous monitoring and in-field feedback throughout the vehicle’s lifecycle are now critical, particularly as more leading-node devices are brought into automotive applications.
For these reasons, chipmakers increasingly are adopting in-field testing and on-chip monitors, along with machine learning-based software to see if actual device performance mirrors that of the predicted values and to determine how accurately degradation and aging can be predicted. Virtual testing with digital twins will play an important role in these predictions, as will shift-left testing involving more at-wafer stress testing to precipitate latent failures and ensure known-good-die before advanced packaging.
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