LLMs for chip design; CIM accelerators; polaron crossover in tellurene; M3D FPGA w/BEOL config memories; ASIC AI chips for homomorphic encryption; loss processes; sliding ferroelectrics.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Thickness-dependent polaron crossover in tellurene | Rice, Lawrence Berkeley National Laboratory, MIT, Argonne National Laboratory, ORNL, Purdue, Stanford |
| ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation | NVIDIA |
| Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories | Georgia Tech and UCLA |
| Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators | TSMC and National Tsing Hua University |
| Leveraging ASIC AI Chips for Homomorphic Encryption | Georgia Tech, MIT, Google and Cornell University |
| Where Do the Electrons Go? Studying Loss Processes in the Electrochemical Charging of Semiconductor Nanomaterials | Delft University of Technology |
| Superconductivity from Domain Wall Fluctuations in Sliding Ferroelectrics | University of Cambridge and Argonne National Lab |
Find all technical papers here.
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