Chip Industry Technical Paper Roundup: July 16

On-chip communication for programmable accelerators; neuromorphic roadmap; RTL optimization; DRAM read disturbance; programmable quantum emitter in Si; bandgap tuning; 2D ultralow temp, high performing quantum; 3D integrated metal-oxide transistors.

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New technical papers recently added to Semiconductor Engineering’s library.

Technical Paper Research Organizations
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures Columbia University and IBM
Roadmap to Neuromorphic Computing with Emerging Technologies University College London, Politecnico di Milano, Purdue University, ETH Zurich and numerous other institutions
Three-dimensional integrated metal-oxide transistors KAUST
ROVER: RTL Optimization via Verified E-Graph Rewriting Intel Corporation and Imperial College London
Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance ETH Zürich and TOBB University of Economics and Technology
Programmable quantum emitter formation in silicon Lawrence Berkeley National Laboratory and University of California Berkeley
Strain Driven Electrical Bandgap Tuning of Atomically Thin WSe2 University of Toronto, University of Tokyo, and Stanford University
Electrically tunable giant Nernst effect in two-dimensional van der Waals heterostructures EPFL and National Institute for Materials Science (Japan)

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