SRAM substitute; 3D photonic integration; 3DIC partitioning; CFETs design; EFO errors in wirebonding packaging process; 6G survey; multi-party computation for securing chiplets; microfluidic-cooled 3DICs.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache | Georgia Tech and Univ. of Virginia |
| Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links | Columbia Univ. Cornell Univ., Air Force Research Laboratory Information Directorate, Dartmouth College |
| PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation | Seoul National Univ. and Ulsan National Institute of Science and Technology |
| Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) | National Yang Ming Chiao Tung Univ. |
| Large-Scale Integrated Photonic Device Platform for Energy-Efficient AI/ML Accelerators | HP Labs, IIT Madras, Microsoft Research and Univ. of Michigan |
| A Comparative Study on Various Au Wire Rinse Compositions and Their Effects on the Electronic Flame-Off Errors of Wire-Bonding Semiconductor Package | Hanbat National Univ., Seoul National Univ. and Chungnam National Univ. |
| A Survey on Advancements in THz Technology for 6G: Systems, Circuits, Antennas, and Experiments | UCLA |
| Garblet: Multi-party Computation for Protecting Chiplet-based Systems | Worcester Polytechnic Institute |
| Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs | Univ. of Michigan, Shanghai Jiao Tong Univ. and Univ. of Virginia |
Find more semiconductor research papers here.
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