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Chip Industry’s Technical Paper Roundup: Jan. 17

Hardware trojans at four process technologies; eFPGAs; RISC-V based DNN accelerator; in-DRAM processing; quantum interconnects; directly printing electronic circuits onto curved surfaces; quantum processors with Josephson parametric amplifiers; in-field test Of A CAN controller; making thin films of perovskite oxide semis.

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New technical papers added to Semiconductor Engineering’s library.

Technical Paper Research Organizations
Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations Max Planck Institute for Security and Privacy, Université catholique de Louvain (Belgium), Ruhr University Bochum, and Bundeskriminalamt
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU Ecole Polytechnique Montreal, IBM, Mila and CMC Microsystems
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM ETH Zurich and TOBB University of Economics and Technology
On-demand directional microwave photon emission using waveguide quantum electrodynamics MIT
Curvilinear soft electronics by micromolding of metal nanowires in capillaries North Carolina State University
Readout of a quantum processor with high dynamic range Josephson parametric amplifiers Google Quantum AI, University of Massachusetts, Auburn University and UCSB
A Systematic Method to Generate Effective STLs for the In-Field Test of CAN Bus Controllers Delft University of Technology, Cadence, and Politecnico di Torino
Freestanding epitaxial SrTiO3 nanomembranes via remote epitaxy using hybrid molecular beam epitaxy University of Minnesota Twin Cities, Pacific Northwest National Laboratory, and University of Wisconsin–Madison
Duet: Creating Harmony between Processors and Embedded FPGAs Princeton University

If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting links to papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate.

More Reading
Technical Paper Library home
Chip Industry’s Technical Paper Roundup: Jan 3
Area-efficient RISC-V decoupled vector coprocessor for HPC; rowhammer mitigation; HW accelerator; epitaxial graphene platform; power electronics; MTJ for stochastic computing; clock gating; paper-thin solar cells added to any surface; data transmission using inverse-designed silicon photonics.



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