Better measurement of edge defects can enable higher yield while preventing catastrophic wafer breakage, but the number of possible defects is increasing.
Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages.
This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the growing emphasis on reliability in multi-chip/chiplet designs, where a latent defect can turn multiple chiplets into scrap. Finding the root cause of a defect, and ensuring that it’s not systematic and reducing the yield on all wafers, can result in months of delays.
There are numerous reasons why it’s so hard to produce high-yielding chips at the 300mm wafer edge, including wafer uniformity, process variation, and multi-layer effects such as film stress. Maintaining across-wafer uniformity is particularly daunting. Leading-edge designs can require up to 1,000 process steps per wafer, including patterning, deposition, etching, CMP, and plating. While electrostatic chucks and wafer edge rings are designed specifically to improve the uniformity of processes, conditions at the edge tend to drop off nonetheless. Both dry and wet processes are used, but wet etches also can damage the wafer edge — a critical concern in 3D NAND processes that are rapidly moving to hybrid bonding.
Worst case, edge defects can be the culprit behind wafer breakage, which is especially costly. “Edge defects can be a major cause of wafer breakage in the fab, which disrupts the production line and can lead to very high cost,” said John Wall, UK site manager at Bruker. The cost is associated with product loss, time to clean the process chamber, and most critically, the need to find the root cause of the breakage.
“Wafer breakage most often occurs during aggressive processing steps, such as rapid thermal anneal or CMP,” said Wall. “But the defects, which are the precursor for the breakage, can be formed at many different process steps prior to that step — for example, by handling errors that impact the wafer edge. If these defects are not present on the wafers, then the wafers would not break during RTA or CMP.”
Boosting the yield of chips on the wafer edge can provide significant return, depending on the specific device and volume. “There is still a lot of yield potential on the edge of the wafer,” said Dieter Rathei, CEO of DR Yield. Depending on the process, the focus on improving edge yield can require the resources of teams of process, product, and yield engineers, which can be costly. “There’s a lot of yield potential, but it’s basically an economic question of whether the effort to obtain that last percentage of yield gain is cost-effective.”
Wafer edge defects
Defects at the wafer edge include particles, chipping, scratches, thin-film peeling, among others. During product development stages, surface defects — as well as bulk defects in silicon and epitaxial layers, such as lattice voids and slip — must be identified early so they can be caught in high-volume manufacturing. Optical methods commonly use infrared scatterometry to detect hidden defects like pin holes or air pockets. X-ray diffraction imaging (XRDI) can identify epilayer dislocations in Si/SiGe superlattice structures, which influence transistor properties in finFETs and gate-all-around structures. And e-beam metrology using voltage contrast can help identify CD and overlay variability, which can be exacerbated by film stress and warp across the wafer.
3D NAND stacks, in particular, need ways to ensure the memory stacks are known good before bonding multiple stacks of memory on the logic periphery wafer. “People are using double patterning with double etch (litho-etch, litho-etch) in manufacturing, but the final electrical misalignment in devices from one die to another is a function of lithography — but also etch patterns, film uniformity, and CMP uniformity,” said Tomasz Brozek, technical fellow at PDF Solutions. The wafer edge region, because of issues of warping or process non-uniformity in etch and CMP, for instance, can have the greatest variation.
“Using design-for-inspection test structures and an e-beam probe with voltage contrast, it is possible to measure the structures electrically to identify the tiniest variations in alignment (overlay) and critical dimension linewidth across the wafer,” Brozek said. “Because you want to stack good die on good die, you want to know the electrical properties before you stack the chips. But it is being done.”
There are other variation problems in 3D NAND manufacturing, where the stacking of hundreds of film layers also increases the opportunities to damage wafer edges. In particular, very long wet etches can cause residues, roughness, and damage along the wafer edge, where material may flake off, drift to other areas, and create defects that cause a semiconductor device to fail.
The transition to stacked chips in advanced packaging applications with 2.5D and 3.5D configurations puts tight constraints on CMP steps that control the wafer edge profile. Here, edge roll-off must be consistent from wafer to wafer because the profile at the edge is particularly important to bond quality.
Starting wafers
Wafer manufacturers, as well as chip manufacturers, use unpatterned wafer inspection tools to determine the quality of so-called bare silicon, epitaxial wafers, SOI, GaN on silicon, and silicon carbide (SiC) wafers. “The defect detection requirements vary between different substrate types. For example, in silicon wafers, the inspection requirements for epi wafers used at leading-edge nodes have far stricter process control requirements with minimum defect size requirements going into nanometer range,” said Burhan Ali, senior manager of product marketing at Onto Innovation.
Unpatterned wafer inspection is typically performed using optical image-based or laser scatterometry-based methodologies, which can effectively catch frontside and backside wafer surface defects such as particles, scratches, and pits. Bare wafers that meet or exceed process specs are shipped to the fab, which typically performs incoming quality checks using the same inspection methods.
Unpatterned inspection also is deployed throughout the fab to monitor process tools to check for particles or other contamination in the fab production line (so-called dummy wafers). Additionally, substrate manufacturers inspect for bulk defects using technologies such as infrared scatterometry or X-ray diffraction imaging to penetrate through the wafer surface and detect defects like pin holes or air pockets.
Inspecting wafer front, back and bevel
Patterned wafer inspection platforms are used to detect defects on the frontside, backside, and bevel (rounded edge) of wafers (see figure 1). “Bevel inspection on both bare and patterned wafers is typically performed using brightfield and/or darkfield illumination, with coverage from multiple cameras to ensure there are no blind spots on the top bevel, apex, and bottom bevel of the wafer,” said Ali. “The wafer is spun to acquire the entire bevel image, from which the defects are classified.”
Fig. 1: A wafer edge image shows the bevel, apex, and bulk silicon regions, as well as a backside defect. Source: Onto Innovation
In-line optical inspection typically is used to detect excursions in processes and to differentiate good die regions vs. defective die regions. “Some of the more popular ones are golden die comparison, die-to-die comparison, and CAD based inspection,” said Ali.
Automatic defect classification (ADC) commonly employs machine learning algorithms to improve classification accuracy and speed. Advanced ADC is used across all surfaces, backside, frontside, and the bevel — including the notch. “A faster time to result is desired by customers to optimize their processes and minimize the time spent on review,” said Ali. The wafer notch is used to precisely orient wafers inside process tools. But the indentation on the wafer edge further reveals the crystalline orientation of the silicon lattice (111, 100, or 110 orientations), which device engineers choose to optimize electrical properties of the device.
One of the most common defects on the wafer backside is a hotspot.[1] During deep UV or extreme UV lithography, backside particles are known to alter depth-of-focus during patterning. Also, backside defects can cause process non-uniformity during etch and ion implantation processes. In the extreme, backside particles also can cause wafer breakage as the wafer is pulled flat on an electrostatic chuck.
Wafer bevel treatments also can be associated with particle issues. “You have all kinds of treatments on the bevel of the wafer, and maybe even particles coming from the backside making their way over the edge,” said DR Yield’s Rathei. “For instance, you have bevel effects from the EBR (edge bead remover), and there are litho patterning defects because there is breakdown at the edge, so lithography overlay and CD errors are more significant.
When backside particles travel to the frontside devices — whether during handling, processing, or transportation in front-opening unified pods (FOUPs), they have the potential to become killer defects. The edge bead removal process removes the bead of photoresist or developer that forms with wet chemistries. Other processes in lithography track systems include backside wafer cleaning and drying prior to wafers transitioning to the next process step, often plasma or reactive ion etch (RIE) chambers.
Variation in electrical performance of finished die becomes especially important in advanced packaging, where chiplets of the same type (such as HBM4) are paired together and stacked, heterogenous chiplets (such as SRAM and processor) are stacked, or heterogenous chips like HBM and processors are interconnected laterally.
Because so many wafer edge defects can be caused by wafer centering errors in process chambers, it is critical to have sensors to establish a wafer is centered on its chuck each time. “A Teach sensor helps determine how centered a wafer is placed in an etch chamber, for example,” said Vidya Vijay, senior program manager of WaferSense at Nordson Test & Measurement. “Precise centering is critical. Any shift from the center can cause severe yield issues down the line. So it trains the robot and end effector to place a wafer in the center.”
For deposition processes, a capacitive sensor is used to ensure the exact same gap between the showerhead and pedestal in deposition chambers, where each 300mm tool typically has multiple chambers. “This gap is a very critical process criteria because the repeatability and reproducibility of deposition thickness and uniformity depends on a consistent gap for every wafer,” said Vijay.
Lattice defects
With the transition to 3D structures, such as finFETs, gate-all-around FETs, and multi-layer superlattice structures, epitaxial layers must be monitored for quality.
“For micro-defects, inspection after epi growth is extremely important,” said Bruker’s Wall. Microdefects formed during epi layer growth (a CVD process) can cause lattice mismatch, dislocations, and slip. These are crystalline defects where, if the epilayer growth is out of control, then the defects can form.
“You can get relaxation or release of strain in the material, in the silicon/silicon germanium superlattice,” said Bruker’s Wall. “The XRDI technique is really sensitive to these types of defects. We align on a diffraction plane from the crystal planes in the wafer. Even if a single atom is missing in the silicon lattice, it will distort the crystalline lattice, creating a strong strain field that can extend tens of microns. If you scale that up, slip is when whole crystal planes that have moved and is strain relieved.”
The key is to capture the onset of strain relaxation in superlattice structures. “XRDI is sensitive to the onset of relaxation, so we see the kind of formation of dislocations, in some cases, with good contrast. It offers a new set of eyes to see that to be more sensitive to that onset of relaxation because at the onset, your process is by definition out of control, said Wall.”
Hybrid bonding and edge rolloff
Hybrid bonding requires tight process control — especially prior to the bonding process, as any particle on the surface of wafers to be bonded can lead to void formation. “As the critical dimensions and pitch for copper pads shrink, ever-smaller particles can lead to yield-killing voids,” said Onto Innovation’s Ali.
In the case of wafer-to-wafer bonding, which is the most common hybrid bonding method used today, optical inspection tools with higher sensitivity are needed to detect these smaller defects. Additional inspection steps are deployed after bonding to ensure that bonding is void-free between the dielectric-to-dielectric and Cu/Cu surfaces.
Another optical technique that is gaining increased usage for advanced packaging is white light interferometry (WLI), a subset of optical profilers. WLI is non-destructive with a wide field-of-view of 2 millimeters, while offering sufficient lateral and vertical resolution to characterize the wafer edge roll off.
“The roll off plays an important role in how well the wafers bond,” said Samuel Lesko, director of technology and applications development at Bruker. “For instance, usually these wafers have gone through multiple CMP steps, so it’s important to keep track of the wafer topography — how fast it drops, and the length of the drop. Optical profilers have extreme nanometer sensitivity vertically, which helps to reproducibly measure roll off at different angle around the wafers as a quality control before bonding.”
Lesko added that both white light interferometer and AFM have their roles in characterizing CMP process, where copper will polish faster than the dielectric, causing some copper dishing. That dishing cavity must be extremely uniform across the wafer to ensure all copper connections are made upon anneal.
Conclusion
To maximize yield of die at the wafer edge, fabs are employing a combination of metrology and inspection methods, complemented by ML algorithms to provide faster time to results. The move to hybrid bonding imposes new restrictions on wafer edge properties, which must be met to provide high-yielding wafer-to-wafer bonds.
Reference
Related Reading
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Many More Hurdles in Heterogeneous Integration
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