Design Rules Explode At New Nodes

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at GlobalFoundries; Michael White, director of product marketing for Calibre Physical Verification at Mentor Graphics, and Coby Zelnik, CEO of Sage Design Automation. What follows are excerpts of that roundtable discussion.

SE: If we had EUVby now, would there be fewer design rules?

Capodieci: If it comes it 10nm, which it won’t, it would still be sub-resolution. EUV is 15nm. The design rules are not driven exclusively by lithography. They’re driven a lot by patterning, which involves more than lithography. It starts with litho as etch components and metallization. All of these components interact with each other. The function, the form will drive the subsequent steps. The problems are not necessarily with litho, though. The real question is whether the patterning will hold together to create the devices and connect all the devices together. The design rule complexity is driven more than 60% to 70% by patterning.

SE: But isn’t that directly related to lithography?

Capodieci: No, it’s more about etch and CMP.

White: Even when EUV hits, if it’s at 7nm it will have to be double patterned. Given other aspects of EUV, it will bring with it a whole bunch of design rules related to EUV imaging.

Capodieci: But it’s not direct cause and effect. Design rule complexity is driven by the patterning. The patterning is really nature telling you, ‘This is how I work.’ So you can create a very large set of often-inconsistent design rules because the tools allow you to specify them, but then the question is how you do a good design that conforms to the laws of nature with etch and CMP. How do you create a design system that drives the physical design into a good spot of what nature allows? If you look at directed self-assembly, you only can do a certain alphabet of patterns. This is happening also for double- or triple-patterning. Only a certain set of shapes and forms can be manufactured. You need to focus on what you can make, rather than what we cannot make. That will take generations of layout designers, assisted by tools, to determine if we can create a functional design with different shapes. That’s how it will be going from 10nm onward.

Shumarayev: If you look at this in the context of time to market, from the multitude of designs you have to conform to this set of patterns. You’re under time-to-market pressures, you have some goals and estimations and it’s vastly different than what you expected. I’ll use the word ECO in the context of a design, and that’s becoming non-trivial. You cannot create a patterning structure here. In deep-submicron it is an enormous cycle. The world is changing from, ‘Here is a space and you can put any pattern here connecting from point A to point B.’ That isn’t possible anymore.

SE: This has been talked about for a long time, though, right? You can’t push the analog pieces into the design.

Shumarayev: You can’t ask humans to 3D visualize it and keep the electrical computation engine going in your brain. It’s fertile ground for EDA, though.

White: At 10nm it looks like the industry will roll with the same methodology we’ve had forever. It works fine for digital. For custom, we’re going to have to have more things like an in-design solution or in Calibre real-time where the customer is getting real-time feedback about design modifications so they understand where they are running awry of the 6,000 design rules out there. A designer cannot keep all of that in his mind as he is trying to do layout. That is going to have to become standard practice using real-time feedback to make a custom designer more productive.

Shumarayev: You can’t wait until the whole cycle is complete to uncover your 3X performance.

White: Those real-time engines are going to have to be more than just DRC. You’re going to have to have patterns, litho.

Shumarayev: Yes, and thermal effects of different device types. Noise is a big deal, too, from the silicon point of view. And then if you go to 2.5D there are no good methods right now, even from the substrate levels.

Zelnik: We need a better platform for being able to explore design rules early on to determine what structures work in the library space, the routing space, and take that knowledge into the design exploration rather than thinking only about the specifics of the fab. We also need to be able to provide any changes that come in or any updates faster, and to be able to verify the deck. In order to verify anything you need a reference to compare it with. A design rule today is a manual written in freeform English in Word. How do you verify against this presentation and build tools to specify these design rules? You need to formally be able to do things with it—either pass it onto the router or verify the DRC checks against it.

SE: We’ve always had design rules at every new node, but they’ve been relaxed as processes matured. Will that be the case at 14nm, 10nm and beyond?

White: I don’t see them being relaxed.

Capodieci: The answer is absolutely not. It won’t happen. You realize that some of the rules were not necessary or there was too much guardbanding. That won’t happen. Relaxing design rules means you allow new structures to be present in your physical design, which means you allow a combinatorial vast number of interaction effects to occur. And you’ve worked so hard that you’ve eliminated all these interaction effects. At 20nm, who is going to relax a set of decomposition rules just to fail the decomp algorithm fail and cause more stitching.

White: We’re not seeing any relaxation of design rules even at 28nm. Once a foundry gets a different process dialed in and design rules describing that process are all self-consistent, that can’t happen. Each foundry has finite resources. They don’t have the bandwidth to go back and look at that node and spend time trying to understand what design rules can be relaxed a little bit. What I do observe, though, especially for the large fabless companies, is a conversation that, ‘Okay, can I have a waiver for this particular pattern?’ We do see a growth in that kind of conversation because they built something on a previous test chip and it came through fine.

Capodieci: That’s the right answer. There is no ‘Get out of jail free’ card. But in select cases, you can get out with a waiver.

White: We’ve seen a big increase in that kind of partnership between a foundry and a fabless company, so the next time they instantiate that same IP they don’t see a DRC result associated with that anymore. There’s also an automated way for the foundry to see that when there’s a tapeout.

Shumarayev: There are thousands of waivers. How do you automate that? It’s a non-trivial question.

To view part one of this roundtable discussion, click here.
To view part two of this roundtable discussion, click here.