Analog circuitry stopped following Moore’s Law a long time ago, but that hasn’t always helped.
The gap between analog and digital reliability is growing, and digital designs appear to be winning.
Reports show that analog content causes the most test failures and contributes significantly more than digital to field returns. The causes aren’t always obvious, though. Some of it is due to the maturity of analog design and verification. While great strides have been made in digital circuitry, analog design automation and verification methodologies have lagged. In addition, leading-edge nodes make it increasingly difficult to construct reliable analog circuitry.
“The analog blocks do account for a large percent of chip failures,” says Scott Guyton, manager for solutions architecture at Mentor, a Siemens Business. “This is due to high complexity, an error-prone process, full-custom design, variability, limited systematic verification to assess robustness, and much less automation compared to its digital counterpart.”
Others are more direct in their assessment. “Analog is a dinosaur waiting for a meteor,” says Steve Lewis, marketing director for Cadence.
There are statistics to back this up, as well. “One way to track the progress of analog design methodology is the percent of field failures due to analog elements of a design compared to other elements,” says Art Schaldenbrand, senior product manager at Cadence. “At the VLSI Test Symposium, the report was that 95% of field failures are due to the analog elements of the design. So, there are significant issues.”
However, not everyone sees this problem. “Analog is hard,” admits Sunil Bhardwaj, senior director for Rambus‘ India design center. “It requires investment from designers. Interfaces are the way in which a chip interacts with the rest of the world, and that is analog by definition. We do not see that portion of the design contributing asymmetrically to failures.”
It’s also important to distinguish between good and bad analog implementations. In effect, not all analog is created equal.
“Our designs are about 90% mixed-signal on the physical layer side, where the PHY is one of the more difficult pieces of IP that has to be developed for a high-speed SerDes or memory interface,” says Frank Ferro, senior director for product management at Rambus. “Reliability is the first and foremost requirement for these interfaces. To work in a data center, where it has similar temperature requirements to automotive, it has to be reliable for seven-plus years of operation. We have to meet very strict standards, be it analog or digital.”
But analog requires a different approach, and much of that stems from designer experience rather than a heavy reliance on tools. “The lack of automation in analog design puts more burden of quality and performance on the experience of the individual designer and design teams versus that of digital design teams,” says Guyton. “This requirement results in much higher design costs due to longer design cycles, custom flows, and higher resource costs.”
The situation
Progress continues in making analog easier and more predictable. “Traditionally, analog design was considered a form of art best left to those few who liked to tinker with sizes of transistors,” explains Manuel Mota, product marketing manager at Synopsys. “Tools to support analog design automation and systematization generally were not available, leading to long and arduous development phases and possibly deviations from expected targets. However, design flows have evolved to enable higher quality designs through partial automation of the design and verification efforts, simpler and more accurate annotation of silicon effects at earlier phases of the design cycle, and more accurate device models and simulators.”
Unlike digital circuits, analog circuitry does not scale well. “Most technology scaling is tuned for the digital world,” says Bhardwaj. “A lot of the focus, at least from the transistor technology development, is around switches. This is a very digital notion. One of the big challenges for the analog developer is being able to understand the analog implications of shrinking geometries. This is hard and not always in the best direction for an analog designer—more mismatch, more variability. And then you add on top of that the EDA tools don’t always comprehend that, and these make the design hard. We can only compensate by having experienced engineers.”
Scaling does not apply to analog in the same way. “Generally speaking, the extreme advanced nodes do not have a major impact on the transistors in the analog portion of the design,” points out Steve Lewis, marketing director for mixed-signal at Cadence. “Often, these transistors are larger to make sure that loads, power distribution, and signal fidelity are all well maintained within the application. The small nodes do impact the digital cores and signal processing circuitry. But that is why we have mixed-signal simulation, so that our customers can mix the domains together, each maintaining the right transistor size for the application at hand.”
But even then it has an impact. “Analog design is driven by process parameters, including supply voltages, transistor gain, thresholds and fT,” says Guyton. “These vary with each emerging technology. With the emerging trends towards lower power consumption in IoE, energy efficiency is a critical figure of merit resulting in more stringent clocking requirements, lower noise, and stability with temperature. As we move to smaller process nodes with lower voltages and lower power requirements, maintaining the same noise performance is very challenging. Low power and low noise are conflicting requirements. This makes understanding device noise and its impact even more critical than in previous generations.”
A slowdown in device scaling could help analog catch up, as well. “The end of Moore’s Law will start to have a significant impact,” says Benjamin Prautsch, group manager for Advanced Mixed-Signal Automation at Fraunhofer IIS/EAS. “There is less pressure to move analog content to the newer nodes, which is both time-consuming and expensive. But there are secondary advantages to staying with older nodes. As those nodes become more mature, the knowledge about them will increase, and that will decrease the desire or need to more to the newer technologies. At some point the integration of RF and analog components will stop.”
Cadence’s Schaldenbrand says that designers have several options for implementing analog functionality in advanced node processes. Among them:
Digitally assisted analog
There is one other alternative, as well. “Analog blocks have shrunk in area and power consumption in ways that may be surprising to many,” says Synopsys’ Mota. “It may be argued that, for some functions, area and power consumption have scaled at rates consistent with Moore’s Law. We can show examples for a host of different analog functions ranging from data converters, to PHYs, and even RF transceivers. Such progress is not achieved simply by optimizing transistor sizes for the new process, which is not enough since analog designs seldom make use of minimum sized transistors due to analog performance (linearity) and matching concerns. Instead, analog designers develop new architectures to deploy the same function. Rather than going against the ‘digital’ nature of advanced processes, analog designers take advantage of the abundance (and tiny area) of digital gates to implement ‘digitally assisted analog functions.’ The analog block is simplified at the expense of its raw analog performance, but includes knobs that enable an embedded digital function to analyze the actual performance and to calibrate and correct the operation, so as to achieve the correct performance in each condition.”
Rambus is going in a similar direction. “When we look at the analog circuit, they have significant digital content,” says Bhardwaj. “We often rely on digital techniques to assist the analog to deal with variation, to deal with a variety of configurations, to deal with calibration and training. This is best done in digital. Designs are becoming mixed-signal, and a lot of analog has digital components to calibrate analog to improve their robustness. We always have to consider architecture. There have been a lot of advances in the architecture of analog designs in which we use digital techniques, especially on the power front, to improve the performance of the analog circuits.”
Test and verification
There are three primary reasons for analog failures in the field. The design may not have been properly verified, such that variation in the field causes a failure; chip test did not catch that a particular device did not conform to its operational parameters; or parametric drift in the field could cause a device to go out of tolerance.
Compare the level of automation available to digital designers for verification to that available to analog designers. “Digital designers perform their regressions nightly and track progress on coverage,” says Schaldenbrand. “Analog designers don’t even have tools to perform verification. For example, instead of assertions to report pass and fail, many analog designers still need to manually ‘eyeball’ the waveforms to make decisions about the functionality of their designs.”
This makes analog design more expensive. “The EDA industry has done a great job in enabling multi-billion transistor designs,” says Bhardwaj. “However, analog verification still relies a lot on techniques that were developed many years ago – SPICE. As the content of analog increases with bandwidth requirements and interface requirements, we do not have tools that can handle that complexity. So the investment of the design community, the design engineers and their experience, and most importantly their time, goes into analog verification.”
EDA companies have long seen this as an opportunity. “There have been a couple of traditional ways to solve the analog verification problems and there are a couple of emerging trends that borrow from our digital brethren,” explains Lewis. “On the former, there is the usage of corners/statistics simulation and modeling, which can help the designer center their design to achieve maximum density while maintaining enough ‘margin’ in the design to soothe a lot of the variation that can occur.”
Mota agrees. “Achieving high design coverage requires hundreds of thousands of Monte Carlo runs per corner, which is not practical. Fortunately, modern techniques to handle large variability, based on high sigma analysis, such as sigma-amplification and others reduce the simulation time significantly, down to only hundreds of runs, for the same coverage.”
For new techniques, Lewis points to the emergence of reliability and fault testing for the analog side. “Over the last few years, new ISO standards have begun to emerge to assist in the description of analog faults, particularly for the auto industry, which relies heavily on analog circuitry, to provide analog designers a path to extend the testing cycles of the analog design, and thereby provide a deeper confidence in the long-term viability of the analog part.”
This will become better defined this year. IEEE P2427, “A Standard for Analog Defect Modelling and Coverage,” will define how to model faults and calculate test coverage. The standard should accelerate the development and deployment of tools for analog fault simulation of test coverage in 2019.
A white paper written by Steve Sunter, engineering director for mixed-signal DFT at Mentor, points out that test time per analog transistor has not decreased. In contrast, there has been a remarkable improvement for the digital content. “For mixed-signal ICs, test time for the analog portion can dominate total test time. For mixed-signal automotive ICs, overall test quality has steadily improved, until recently. Whenever results asymptotically approach a limit, it indicates that a new tactic is needed to significantly improve results.”
Fig 1: Defect rates for automotive ICs and cause of failures. Source: Mentor
Test is a challenge for analog. “The ability to differentiate ones and zeros and to come up with tests, as opposed to being able to differentiate between gain and operating ability at multi-gigabit speeds, are very different things,” says Bhardwaj. “We have a lot of techniques around DFT and scan that are able to test the functional logic, but analog relies on the ability to test at high speed, and those tests are complicated and take time. They require lab characterization and at an e-test or wafer-test level it is quite difficult to be able to test for all of that. There are techniques that are coming, similar to digital assist for analog, which rely on digital signals to be able to test the analog robustness.”
To do this, sensors are inserted into the chip, such as temperature sensors, or corner performance sensors. “They exist as analog designs, and when properly used they are able to calibrate and offset the performance of the analog system so that it can adjust,” adds Bhardwaj. “If a chip is good or not, or if there is process variation, a lot of designs have digital assist that allows them to calibrate and handle the variation.”
Once inserted, those sensors can help the chip to adapt rather than fail. “Given that aging processes are complex and often difficult to fully predict, many chip designs today are often over-designed to ensure adequate margin to meet requirements for reliable lifetime operation,” says Stephen Crosher, chief executive officer for Moortec. “If the aging processes could become more deterministic—or better still, if you can monitor the aging process in real-time—then you can reduce the over-design and potentially develop chips that react and adjust for aging effects, or even predict when chip failure may occur.”
Conclusion
Analog design will always be more difficult than digital, and to companies that have chosen to excel in this area, it can provide them with a protective moat.
“Process evolution as dictated by Moore’s Law is not a limitation for analog content,” says Mota. “It opens the door to new and creative architectures, and as such it is an opportunity. Challenges remain, especially in terms of design automation for productivity. Even if the ultimate goal of generalized automatic analog design synthesis and optimization still seems far away, it is an area that is evolving.”
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Back in the day we used to reject the atypical devices in a population before trying to pull model fitting data, and never looked back. The idea was if the transistor was bad, oh, well… ink the die. Fine for a hand crafted dual op amp or other SSI analog. Chase the dirt out, later.
If you want to bury a bazillion of little analog blocks inside a low-test-access design, you can easily embed a lot of “victims” and not know some of them got hit. There has been no real attempt at true analog fault coverage that I’ve seen (and I’d rebel against using it anyway – tough enough to get everything right across PVTM, in the normal device range – forget adding test access gingerbread to something operating up against the process bandwidth limit).
I’ve done designs where analog complexity and high reliability indicated a need for some test mux access. But it did become a chore that added nothing to performance, seemed to offer little upside when we got to test, and added a bunch of interaction potential that ate a lot of designers’ time to challenge & prove out.
At some point you have to push back on the fab and tell them to quit putting dirt in your transistors. But with most folks being “fabless sharecroppers”, good luck with that. So you’re left with the job of coming up with a strategy that involves (a) learning to like the taste and (b) eating less of it.
Do I have a solution? No. Other than to stick with the kind of design I know, and fortunately, -my- customer base likes.
The bit about having process corner sensors makes no practical sense. Circuits are designed to have local matching and designed robust enough to not care about process variations such as vt and Kgm etc. Global calibration is a solution looking for a problem.