Manufacturing Bits: Aug. 24

Panel packaging consortium
Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies.

Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Panel Level Packaging Consortium 2.0.

In advanced packaging, the idea is to assemble and stack complex dies in an IC package, creating a system-level design. To make some package types, the processes are conducted on 200mm or 300mm round wafers.

Many are trying to develop IC packages on large square panels. A panel can process more packages than a round wafer, which reduces the cost. For example, a 300mm wafer can process 2,500 6mm x 6mm wafer-level fan-out packages, but a 600mm x 600mm panel can accommodate 12,000 packages, according to ASE.

Packaging on a large square panel is significantly more difficult, and mass adoption is not expected anytime soon.

Meanwhile, in 2016, Fraunhofer IZM teamed up with 17 companies to develop the fundamental processes for panel-level packaging technologies. Initially, the focus of the consortium was on the process flow, such as assembly, molding, wiring, cost modelling and standardization. The first incarnation of Panel Level Packaging Consortium ran from 2016 to 2019.

Running from 2020 to 2022, the next phase of the consortium will focus on some major challenges in panel-level packaging. This includes die placement and embedded technology for fine-pitch packages down to 2µm line and space with a potential move to 1µm. Another effort has been on the investigation of warpage and die shift in large format reconfigured panels (18- x 24-inch).

The group has made progress in all areas. Test structures for electrochemical migration tests were also designed in accordance with the IPC standard.

The work is not finished. The group continues to develop “future manufacturing technologies for maximum integration density on the panel level,” said Tanja Braun, group leader at Fraunhofer IZM.

Besides Fraunhofer, the consortium includes Ajinomoto, Amkor, ASM Pacific Technology, AT&S, Atotech, BASF, Corning, Dupont, Evatec, Fujifilm, Intel, Meltex, Nagase, RENA, Schmoll Maschinen, Showa Denko Materials, and Semsysco.

Photonics packaging/test
PhotonicLEAP, a European collaborative project coordinated by Ireland’s Tyndall National Institute, has been awarded over €5 million to develop technologies that will drive down the cost of silicon photonics test and packaging.

The PhotonicLEAP consortium includes Fraunhofer, LPKF Laser & Electronic, ficonTEC, Suss, Bosch, Eindhoven University of Technology, Imec and Tyndall National Institute.

Silicon photonics is promising technology, which enables faster data transfer over longer distances compared to traditional electronics, according to Intel.

Communication over fiber using light has been in use in telecommunications for the past couple of decades due to its ability to carry large amounts of data at extremely fast speeds.

However, silicon photonics promises to increase data transmission speeds, while consuming less power. Silicon photonics makes use of photonic integrated circuits and lasers.

“Light sources (lasers, the engine of photonic components) are very challenging to develop in silicon photonics due to the indirect bandgap of silicon (a horizontal shift between the valence and conduction band of the material),” according to Synopsys. “For light to be generated, a material needs to have a direct bandgap. Therefore, other materials with direct bandgap, such as indium phosphide (InP), are used to create the lasers, and they are integrated in the silicon photonics wafer (chip) to drive the photonic components within the photonic circuit.”

Still, photonics manufacturing is costly, particularly in the areas of packaging and testing, according to Tyndall National Institute. Propelled by funding from the European Union, the PhotonicLEAP program hopes to drive down the cost of silicon photonics packaging and testing by tenfold.

The program will develop new technologies to produce a surface mount technology (SMT) photonics IC package. It will incorporate multiple optical and electrical connections, which can be scaled from low to large volumes.

The project will validate these technologies through two demonstration vehicles–a high-speed optical communication module and a portable medical device for cardio-vascular diagnostics. These technologies will be implemented within the European PIC Packaging Pilot Line, based in Ireland.

“Photonics is the key to unlocking the potential of technologies we need for today’s interconnected world. We need faster, more efficient, greener and cheaper solutions to our increasing usage of technology, which photonics manufacturing addresses,” said Peter O’Brien, a professor and head of photonics packaging and systems integration at Tyndall.

More photonics
The European Union (EU) also has another photonics packaging effort in the works.

Some 31 companies are involved in the project, dubbed the “Advanced packaging for photonics, optics and electronics for low-cost manufacturing in Europe” or APPLAUSE.

APPLAUSE has been in the works for some time. Here’s an update on the program.