Manufacturing Bits: July 10

Semicon West
It’s Semicon West time again. Here’s the first wave of announcements at the event:

Applied Materials has unveiled a pair of tools aimed at accelerating the industry adoption for new memories. First, Applied rolled out the Endura Clover MRAM PVD system. The system is an integrated platform for MRAM devices. Second, the company introduced the Endura Impulse PVD platform for PCRAM and ReRAM. “These integrated platforms illustrate the critical role that new materials and 3D architectures can play in giving the computing industry entirely new ways to improve performance, power and cost,” said Prabu Raja, senior vice president and general manager of Applied’s Semiconductor Products Group.

ASM International has introduced its Previum process module for 300mm integrated pre-deposition surface cleaning, which improves the performance of deposited films. Integrated into ASM’s epitaxy platform, the Previum surface cleaning module enables epitaxial depositions for advanced node channel and source/drain engineering applications.

Coventor, a Lam Research Company, has announced the availability of SEMulator3D 8.0 – the latest version of its semiconductor virtual fabrication platform. SEMulator3D 8.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development. “The new Process Window Optimization (PWO) feature performs process window optimization without the requirement for time-consuming and expensive silicon wafer tests,” according to Coventor. “This capability, in conjunction with existing SEMulator3D features, enables earlier understanding of critical process factors and their impact on yield.”

Imec has rolled out a dual-damascene 21nm pitch test vehicle relevant for manufacturing the 3nm logic node. With the test vehicle, a 30% improvement in resistance-capacitance product (RC) was obtained compared to previous generations. To pattern the M2 layer, a hybrid lithography approach was proposed, using 193nm immersion-based self-aligned quadruple patterning (SAQP) for printing the lines and trenches, and extreme ultraviolet lithography (EUVL) for printing the block and via structures. The test vehicle implemented a barrier-less ruthenium metallization scheme and an insulator with dielectric constant k=3.0.

Intel has unveiled new building blocks within its advanced packaging portfolio, including a new bridge and 3D technologies. “Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip. A heterogeneous approach gives our chip architects unprecedented flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors. Intel’s vertically integrated structure provides an advantage in the era of heterogeneous integration, giving us an unmatched ability to co-optimize architecture, process and packaging to deliver leadership products,” said Babak Sabi, Intel corporate vice president of the Assembly and Test Technology Development group.

JSR Micro has begun construction on a new state-of-art facility in Hillsboro, Ore. The full investment for the project is an estimated $100 million and is scheduled to start operations in 2020.

KLA has announced a new defect inspection and e-beam review portfolio. The new 392x and 295x optical patterned wafer defect inspection systems are based on broadband plasma illumination technology. The systems use different wavelength ranges to cover inspection applications for all layers, from shallow trench isolation through metallization. The eDR7380 e-beam wafer defect review system provides fast defect sourcing in development and accurate data during production. “Manufacturing the next generation of memory and logic chips profitably requires unprecedented process control,” said Ahmad Khan, executive vice president of the Global Products Group at KLA. “Device structures are smaller, narrower, taller and deeper, with more complex shapes and new materials. Discriminating defects from benign physical variations—signal from noise—has become an incredibly difficult problem. Our optical and e-beam engineering teams have developed a family of innovative, connected defect inspection and review systems, designed to enable our industry to continue to move forward.”

New materials
The U.S. Department of Energy (DOE) will invest $32 million to accelerate the design of new materials with the help of supercomputers.

The four-year effort will be supported by national labs and universities. Argonne National Laboratory, Brookhaven National Laboratory, and Lawrence Livermore National Laboratory are part of the effort. The University of Illinois, Pennsylvania State University, the University of Texas and the University of Southern California are also involved.

As part of the effort, DOE has awarded the Midwest Integrated Center for Computational Materials (MICCoM) as one of the funded projects. The funding level is $2.5 million per year for the next four years.

The center is led by the Argonne National Laboratory, with co-investigators from the University of Chicago, University of Notre Dame, and University of California at Davis.

The MICCoM mission is to develop computational tools, open-source software, data, simulation methods and validation procedures.

New memories
A group of 19 research and industrial partners in Europe have launched a three-year program for the development of emerging memory technologies for neuromorphic computing.

The project, dubbed TEMPO, is funded by the ECSEL Joint Undertaking. The project will leverage MRAM technology from Imec, FeRAM from Fraunhofer, and ReRAM from CEA-Leti. The goal is to develop spiking neural networks and deep neural network accelerators for eight different use cases, ranging from consumer to automotive and medical applications.