MIS Packaging Takes Off

Momentum is building for IC packages based on an emerging technology called molded interconnect substrate (MIS).

ASE, Carsem, JCET/STATS ChipPAC, Unisem and others are developing IC packages based on MIS substrate technology, which is ramping up in the analog, power IC and even the cryptocurrency markets.

MIS starts with a specialized substrate material for select IC packages. The MIS substrate itself is developed and sold by various vendors. A packaging house then takes that substrate and assembles an IC package around it. Some refer to the MIS substrate as a leadframe.

MIS is different than traditional substrates, as the technology consists of a pre-molded structure with one or more layers. Each layer is pre-configured with copper plating or interconnects to provide electrical connections in the package. All told, MIS supports single- or multi-die configurations, enabling low-profile, fine-pitch packages. It can be used to develop souped-up leaded packages, flip-chip, modules and system-in-packages (SiPs).

Fig. 1: MIS lead frame is pre-molded. Source: Unisem

Fig. 2: IC package using MIS Source: Prismark, Qdos

On the surface, MIS resembles a fan-out wafer-level package. The big difference is that MIS is limited in terms of I/Os and densities. So in reality, MIS competes in the midrange space against some well-entrenched package types.

MIS has been around for nearly a decade, but the market is just starting to take off. “(MIS is) growing in both low- and high-power applications due to advanced routing and reliability properties,” said Mark Gerber, director of engineering and technical marketing at Advanced Semiconductor Engineering (ASE).

In addition, MIS also presents customers with new options, as well as potential replacements for existing packages. “The volumes are increasing over time,” said Nokibul Islam, director of group technology strategy for the JCET Group of companies. “Some of the traditional QFN- or leadframe-based packages can be replaced with MIS because of the line and space capabilities, the electrical and thermal performance, and small form factors.”

In addition, MIS-based packages are being targeted for house chips that go in the cryptocurrency server market. Potentially, the volumes are enormous, but many wonder if or when the cryptocurrency market will dry up.

What is MIS?
MIS was developed around 2010. JCET, one of the early developers of this approach, licensed the technology to a sister company called MISpak Technology.

MISpak, in turn, develops and sells MIS substrates to outsourced assembly and test (OSAT) companies. Other companies, such as ASM Pacific Technology, PPT, Qdos and Simmtech, also sell MIS substrates.

So, OSATs can buy MIS substrates from any number of vendors. Then, in the assembly process, OSATs would incorporate dies within in the MIS substrate, which then becomes the final package.

Fig. 3: SPIL’s Flip Chip – Molded Interconnect System BGA (FC-MISBGA) package. Source: TechSearch International, SPIL

Over time, the MIS business has taken off, as MISpak alone was projected to ship 2.5 billion units in 2017, up from roughly 20 million units in 2010. MISpak claims to have roughly 30 customers in the arena. This doesn’t include shipments from the other MIS players.

Fig. 4: MISpak’s total MIS substrate shipments Source: MISpack

MIS is different than traditional substrates for IC packaging. Many packages use organic substrates, which are multi-layer technologies based on PCB-like materials. In a package, dies are placed on the substrate.

“The interesting feature of MIS technology is that it is made out of a mold compound. The copper traces in the MIS substrate are embedded. So with that, it allows you to have much finer line and space,” JCET’s Islam said.

It also has other properties. “It uses mold compound as the dielectric in between the layers,” said ASE’s Gerber. “When you take that type of leadframe, and then you mold on top of that, the material properties between your mold compound and the leadframe are similar. So it performs very well from a moisture or performance perspective.”

There are several ways to make an MIS substrate. MIS originally comes in the form of a strip measuring 250mm x 70mm. Then the MIS strip undergoes a series of process steps, such as etch, grinding, lithography, molding and plating.

In a one-layer MIS flow, for example, the process starts with a carrier. “On the metal carrier, you do the copper plating to make the traces of the substrate,” Islam explained. “So it’s copper plating, followed by a dry film resist process.”

The resist is stripped. “Then you apply the mold compound. Finally, you grind the mold compound to make sure it meets the desired thickness of the substrate. The last step is to etch the carrier from the panel,” he said.

Fig. 5: MIS Substrate Manufacturing Process Flow Source: JCET

For MIS-based packages, the technology is ideal from 150 to 200 I/Os in low profiles. But the technology is limited to around 25μm line and space, meaning it is geared for mainly mid-range applications. Line and space refers to the width and pitch of a metal trace in a package.

In comparison, a standard-density fan-out package, which is aimed for high-end apps, is defined as a package with less than 500 I/Os and greater than 8μm line/space. High-density fan-out has more than 500 I/Os and less than 8μm line/space.

Meanwhile, the MIS substrate itself is thin. The substrate could be prone to warpage and uniformity issues during a process. Yield and cost are other issues.

“Different applications require specific packaging material in design flexibility and package thickness,” said Ho Kwok Kuen, vice president of marketing in the Material Business segment at ASM Pacific Technology. “Compared to leadframes, ABiT-MIS is capable of producing demanding and complex circuit-designed molded substrates. There are, however, more process steps needed to achieve the design resolution, and we put high focus on achieving a higher yield at each of these individual processes in order to meet the targeted yield at the end of the production line.”

Besides equipment, ASM Pacific Technology also provides leadframes and MIS packaging materials. It refers to these technologies as ASM Buildup Interconnect Technology (ABiT).

Despite the challenges, MIS is growing. “In the last two years, we have seen a spike in interest from many customers looking to use this packaging platform for cryptocurrency mining applications. While MIS is seeing an increasing market share in RF components in telecommunications devices, there are also increasing enquiries from power management and automotive applications as well,” Ho said.

In the market, meanwhile, MIS faces stiff competition. Some refer to the technology as “fan-out,” although MIS doesn’t compete with fan-out. Instead, MIS competes against leadframe-based packages and land grid arrays (LGAs). “The MIS space hovers between what I would call a standard leadless QFN package and a simple two-layer laminated substrate,” said Gil Chiu, vice president of North America at Unisem.

The leadframe group consists of several packaging types, such as quad-flat no-lead (QFN) and quad flat-pack (QFP). A leadframe is a metal frame. A die is attached to the frame and connected using thin wires.

Fig. 6: QFN package. Source: Wikipedia

QFN is mature, cheap and reliable, so there is enormous demand for QFN in analog, automotive, IoT, RF and other markets. Generally, though, QFN is a single-layer technology with limited I/O capabilities. “If you can put it in a QFN, you would obviously do it. A QFN has a lower cost than MIS,” Chiu said. “But when you talk about QFN, you have a limitation in how fine a pitch you can get.”

MIS also competes against laminate packages like LGAs. LGAs consist of a grid of contacts on the underside of a package. LGAs are used for modules, processors and other products.

Fig. 7: Power module LGA package construction Source: Maxim

MIS is cheaper but has less capabilities than LGAs. However, LGAs sometimes suffer from high material and via formation costs, according to Unisem.

So, QFN and LGA have some shortcomings and that’s where MIS fits in. For example, an IC vendor might have an existing chip design at a given process node. The chip is housed in a QFN package.

In this hypothetical example, the vendor faces some challenges. “A customer basically says, ‘I have a current solution. I don’t want to change my die. I don’t want to shrink my die. But I want to shrink the package. And I want to get to a low profile and a smaller size,’ ” Chiu said.

One solution is to move from a QFN-based leadframe package to MIS. Generally, you can take the same die in a leadframe-based package and place it in an MIS substrate. The final MIS package resembles a QFN package, but MIS has more I/Os and better performance.

With MIS, customers can essentially do the same thing with other package types, such as flip-chip, modules and SiPs. “MIS is different. It’s essentially a built-up process. It allows you to frame the metal traces closer. Therefore, you can shrink the package, while maintaining the same die size,” Chiu said. “(With MIS), the customer doesn’t have to spend time or resources to spin a smaller die and reduce the geometries at the die level. With MIS, you can get an extra life out of a product. It allows you to maintain a socket with a known solution. So MIS gives you a smaller package and still gives you the same cost structure.”

Hit or MIS?
For some time, several OSATs have shipped MIS-based packages. Each vendor has a different strategy.

JCET/STATS, for one, has shipped chip-on-lead, flip-chip, modules and SiPs based on MIS technology. “MIS has certain sweet spots. Number one is for high-power, high-thermal applications, but for low I/O counts,” JCET’s Islam said.

So far, the industry has mainly shipped single-layer MIS packages with 25-25μm line/space. “Moving forward, we are also working on finer resolutions. That means finer line and space, as well as much thinner form factors,” Islam said. “Two years down the road, it could go down to 15-15μm line and space.”

In addition, JCET/STATS and others are gearing up for a more advanced process involving a so-called Ajinomoto Build-up Film (ABF) technology. Using laser processing and direct copper plating, ABF enables multiple layers in a substrate at 12-12μm. ABF enables two-, three- and four-layer packages.

Fig. 8: Ajinomoto Build-up Film Source: Ajinomoto

“(With ABF), the process flow is exactly the same. Instead of mold compound, we will be using a heavier film. We can have multiple layers of that type of substrate,” he said. “We expect to a start two- or three-layer MIS using ABF sometime at the end of the year.”

ASE also is ramping up MIS-based packages. ASE’s MIS technology is called C2IM/MIS. “MIS allows you to do some routing in a fairly fine-pitch capability and in a QFN-like format,” ASE’s Gerber said. “(Some customers) have been stuck in QFN, which has limited routing capabilities. When you get a solution that you can actually route at 20-20μm or 30-30μm line/space, that opens up a lot of options for them for one metal layer.”

Besides C2IM/MIS, ASE also offers a competitive technology called “Chip Last Fan Out.” This is not a fan-out wafer-level packaging, however. “It’s essentially a die last process, which means it’s a flip-chip process,” Gerber said. “Chip Last Fan Out is a one-metal layer coreless-based solution that uses two different dielectric materials depending on the routing density.”

In addition, ASE has an alternative to an MIS substrate, dubbed AS3+. “AS3+ is an embedded trace (ET) coreless organic substrate that can offer some similar benefits as the C2IM/MIS solution. In addition, the AS3+/ET substrate allows for three or more routing layers where C2IM/MIS may be limited,” he said. “AS3+/ET may use traditional or ABF dielectric materials. And due to the lack of a core material, it can offer ultra-low inductance between layers to benefit higher speed connections while being cost competitive and reliable due to its manufacturing process flow and its inherent structure.”

For its part, Unisem sees a trio of applications for MIS packages. These packages have an overall thickness of 0.33mm or lower.

The first application is what the company calls air cavity, where a single die is situated inside a package. “We are also using MIS for fine-pitch flip-chip solutions as a go between a laminate versus QFN,” Unisem’s Chiu said. “We are also thinking about doing system-in-package using MIS. It’s a lower cost option to an LGA standard module package.”

For MIS, the big market is power ICs. Another driver is IC packages in cryptocurrency. And going forward, MIS may expand beyond those markets. “The good news is that we are seeing a lot more standard products looking at it,” Chiu added.

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