Chip Industry’s Technical Paper Roundup: Oct 18
RISC-V virtual prototype; on-device training under 256KB memory; HW security in design; compute-in-memory ferroelectric; sub-5nm nanowires arrays; FPGA overlay generation; thermal scanning probe lithography; accelerating long-latency load requests; faster matrix-multiplication; 2D memtransistors.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper |
Research Organizations |
| Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype |
DFKI GmbH and University of Bremen |
| On-Device Training Under 256KB Memory |
MIT and MIT-IBM Watson AI Lab |
| Don’t CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design |
NYU, Intel, Duke and University of Calgary |
| Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes |
University of Pennsylvania, Sandia National Labs, and Brookhaven National Lab |
| Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap |
Northeastern University, Korea Institute of Science and Technology, Gyeongsang National University and others |
| OverGen: Improving FPGA Usability through Domain-specific Overlay Generation |
UCLA and Chinese Academy of Sciences |
| Edge-Contact MoS2 Transistors Fabricated Using Thermal Scanning Probe Lithography |
École Polytechnique Fédérale de Lausanne (EPFL) |
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
*Best Paper Award* |
ETH Zurich, Intel Processor Architecture Research Lab, and LIRMM, Univ. Montpellier, CNRS |
| Discovering faster matrix multiplication algorithms with reinforcement learning |
DeepMind |
| Hardware implementation of Bayesian network based on two-dimensional memtransistors |
Penn State University |
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Linda Christensen
(all posts)
Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
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