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EDA Gears Up For 3D


Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

System Bits: Dec. 15


Building chips skyscraper style With the aim of boosting electronic performance by factor of a thousand, a team of researchers led by Stanford University engineers have created a skyscraper-like chip design, based on materials more advanced than silicon. For many years, computer systems have been designed with processors and memory chips laid out like single-story structures in a suburb whe... » read more