The Week In Review: Sept. 20


By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

The Week In Review: Sept. 13


By Ed Sperling Cadence unveiled its next-generation emulation platform, greatly boosting the speed by up to 60x for embedded OS verification and by up to 10x for hardware/software verification. Overall, Cadence says the platform doubles verification productivity with a capacity of up to 2.3 billion gates. Cadence also reported that its mixed-signal LP flow allowed Silicon Labs to cut its MCU p... » read more

Low-Power CPUs Hitting Their Stride In The Datacenter


By Ann Steffora Mutschler Without a doubt, the cloud has and continues to change the nature of the datacenter, particularly the requirements the infrastructure has to deliver. Diane Bryant, senior vice president and general manager of the Datacenter and Connected Systems Group at Intel, noted during a Webcast last week, “The infrastructure must change in support of cloud-based services.�... » read more

The Week In Review: Sept. 9


By Mark LaPedus SK Hynix’ DRAM fab in China caught on fire. The fire caused one minor injury, but it did not impact the equipment, according to reports. SK Hynix will re-open the fab soon, according to reports. Bob Halliday, Applied Materials’ CFO, gave a presentation at an analyst event, saying: “I think there’s probably more technology inflections going on right now than in years.... » read more

The Week In Review: Sept. 6


By Ed Sperling ARM acquired Cadence’s high-resolution display processor cores, which it helped to co-develop. Coupled with ARM’s own graphics, the move sets up ARM to sell complete subsystems. Cadence also won a deal with SMIC, which is using Cadence’s low-power flow and signoff technology for its 40nm process. Mentor Graphics won a deal with Advanced Wireless Semiconductor Co., whic... » read more

Blog Review: Sept. 4


By Ed Sperling Cadence’s Brian Fuller looks at the opportunity for EDA in the cloud and where it’s most likely to gain traction. How about the PCB? Synopsys’ Mick Posner has moved beyond broad-based design ecosystems. He’s now reaching out to local neighborhoods with FPGA prototypes. Sounds like quality family time. Mentor’s Colin Walls concedes that all non-trivial software ... » read more

The Week In Review: Sept. 3


By Mark LaPedus The cellular chip supplier landscape is littered with corpses. So will 4G lead to the destruction of Qualcomm and Intel? That’s highly unlikely, according to a blog from Strategy Analytics. “With the recent announcement of a multimode LTE chipset from Intel, it seems likely that Qualcomm and Intel will maintain their status as the top two cellular radio chipset suppliers in... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Experts At The Table: Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

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