tag: clock domain crossing

Power Aware CDC Verification Of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
By Mentor, a Siemens Business - 09 Dec, 2015 - Comments: 0

Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic. We will discuss the effects of advanced low power design on CDC design and verification. This paper describes the new CDC issues caused by the addition of power control logic including isolation cells, retention cells, lev... » read more

The Problem With CDCs
By Louie De Luna - 24 Nov, 2015 - Comments: 0

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more

The New Face Of Formal
By Brian Bailey - 29 Oct, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

Next-Generation Power-Aware CDC Verification: What Have We Learned?
By Mentor, a Siemens Business - 08 Jul, 2015 - Comments: 0

Reducing power consumption is essential to mobile and handheld application chips where reduced power contributes to longer battery life while minimally impacting performance. Reduced power consumption is achieved by partitioning an ASIC into multiple power domains, then controlling the power of these domains by switching off power or reducing voltage levels. Reduction of power consumption is fu... » read more

When Things Go Wrong Even When You’re Doing the Right Thing
By Joseph Hupcey III - 28 May, 2015 - Comments: 0

By Kurt Takara and Joe Hupcey III “Isolation. Retention. Level shifters. Dynamic voltage scaling. I’m doing all the right things to reduce the power consumption of my design by adding all of this power control logic. But because of this new low power circuitry, I’m seeing fresh clock domain crossing (CDC) problems that are making my design do all the wrong things; and my trusty old low... » read more

Clock Domain Crossing (CDC): Are We There Yet?
By Ravindra Aneja - 12 Mar, 2015 - Comments: 0

Over the last decade, SoC designs have become significantly reliant on IP reuse to manage the design complexity and meet time-to-market goals. IP-based design and verification methodology is essential but has put an additional verification burden on IP suppliers (internal and external). IP suppliers need to ensure that their IP is exhaustively verified and SoC Integrators need to ensure that al... » read more

Tools And Flows In 2015
By Brian Bailey - 29 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Problems Lurk In SoC Boundaries
By Brian Bailey - 04 Dec, 2014 - Comments: 0

Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

User Case Study
By Joseph Hupcey III - 06 Nov, 2014 - Comments: 0

Whenever more than one clock is employed in an SoC (which is all SoCs), the risk of errors from clock domain crossings (CDC) – signals (or groups of signals) that are generated in one clock domain and consumed in another – is incredibly high. Unfortunately, CDC bugs are nearly impossible to catch with conventional simulations. Thus, all too often they escape into silicon. Debugging them in ... » read more

Where Do We Stand With CDC
By Ann Mutschler - 29 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of [getentity id="22674" e_name="Arteris"]; Shaker Sarwary, VP of Formal Verification Products at [getentity id="22026" e_name="Atrenta"]; Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"]; and Namit Gupta, CAE, Verification Group at [getentity id="22035" e_nam... » read more

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