tag: EDA

The Pitfalls Of Auto-Stitching In Double-Patterning
By David Abercrombie - 22 Sep, 2016 - Comments: 0

Ever since the first double-pattern (DP) odd-cycle error ring was produced on a layout, designers have longed for a magic solution to solve it. Traditionally, the first approach to fixing an odd-cycle error was to move a polygon or a polygon edge to increase spacing to an adjoining polygon in the cycle. Alternatively, you could remove a polygon altogether, or split it into two pieces. All of th... » read more

Cars, Security, and HW/SW Co-Design
By Jeff Dorsch - 13 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Tech Talk: Power Signoff
By Ed Sperling - 08 Sep, 2016 - Comments: 0

Ansys' Aveek Sarkar the challenges of power signoff at advanced process nodes, the impact of over-design, and what's necessary for sufficient coverage. [youtube vid=VQoT2KYW-AM] » read more

Auto Security And Technology Questions Persist
By Ann Mutschler - 01 Sep, 2016 - Comments: 1

While carmakers continue to add increasingly sophisticated driver assist features to new models, semiconductor industry ecosystem players are ramping up their foundation knowledge of what is needed from a technology and security perspective. Fortunately, it appears many existing semiconductor design tools will fit the bill as part of new approaches for automotive design. Mike Stellfox... » read more

Customizable Apps – Avoiding The Pitfalls Of EDA Frameworks
By Dave Kelf - 25 Aug, 2016 - Comments: 0

For those of us involved with EDA tools in the late '80s and early '90s, the word “frameworks” brings back memories of rigid methodology and use models, coupled with CAD complexity. Cadence and Mentor, among others, proposed the EDA framework as a mechanism to provide design revision management coupled with tool flow control (I can already imagine your eyes glazing over). For some situat... » read more

Can Analog And Digital Get Along Better?
By Ann Mutschler - 25 Aug, 2016 - Comments: 1

How to bridge analog and digital is getting renewed attention as the amount of analog content that needs to be processed balloons with consumer and industrial IoT applications. Solving that problem isn’t going to be easy, though. To begin with, digital designers view designs in terms of voltages. Analog designers, in contrast, look at currents. “Unless you can analyze an [getkc id="37... » read more

Putting Design Back Into DFT
By Brian Bailey - 25 Aug, 2016 - Comments: 0

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy. Part one of this two part series about [getkc id="47" comment="Design for Test (DFT)"] looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This co... » read more

Time To Pay The Piper
By Brian Bailey - 28 Jul, 2016 - Comments: 3

The Pied Piper of Hamelin is a German fable about a rat catcher who used his magic pipe to lure away rats. When he was not paid by the town, he used his pipe to lure away all of the town's children. I am not suggesting that exactly the same is true for the semiconductor industry and having not paid [getkc id="7" kc_name="EDA"], but I do not think they have paid enough and they will now have to ... » read more

To 7nm And Beyond
By Ed Sperling - 21 Jul, 2016 - Comments: 4

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold. SE: What do you see as the... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 20 Jul, 2016 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to discuss Moore's Law, the IoT, inflection points and how chip design will evolve in coming years. SE: We are in the middle of possibly one of the biggest transition points we’ve ever seen in this industry. How do you envision things shaking out? De Geus: There is no question that there is an enormou... » read more

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