Chip Industry Week In Review


Dealmaking Amkor inked a 10-year agreement with TSMC to provide advanced packaging and test services in Arizona, tying TSMC’s U.S. fab expansion to domestic OSAT capacity. Trump said in a post that Apple will partner with Intel on chip design and production in the U.S., marking a second reported win for the chipmaker this month. Intel Foundry will also reportedly manufacture 3 million... » read more

Chip Industry Week In Review


Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Chip Industry Week In Review


Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

The Sub-2nm Paradox


Key Takeaways: Process variation and physics are changing semiconductor design, manufacturing, and economics at 2nm and below. Even though new manufacturing processes are being introduced, it's taking longer for them to mature. The focus for many chip designs is faster data movement and more efficient computing, rather than just relying on more transistors per mm2. At 2nm an... » read more

Chip Industry Week In Review


Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Chip Industry Week in Review


Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

AI Accelerator Testing Depends On DFT Innovations


Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

Chip Industry Week In Review


Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

Chip Industry Week in Review


Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes


Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

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