tag: verification

Unified Power Intent
By Ed Sperling - 01 Mar, 2013 - Comments: 0

The next version of the Unified Power Format has been approved, bridging the major differences between UPF/IEEE 1801 and the Common Power Format. For anyone who works in low-power verification, this is very good news. The new standard is the result of an unprecedented collaboration by chipmakers and EDA companies, and the people who devised a solution to this problem deserve a big pat on the... » read more

Clock And Reset Ubiquity: A CDC Verification Perspective
By Various Writers - 28 Feb, 2013 - Comments: 0

Today’s SoC integrates a collection of peripherals, memory, graphics, networking and I/O components that originate from a multitude of sources. It could comprise designs from within the company, from other companies or from third-party IP vendors. These independently developed components come together to enable a rich feature set for the SoC. However, accompanying this abundance of features i... » read more

Ready For 3D-IC
By Various Writers - 28 Feb, 2013 - Comments: 0

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers. To download this white paper, click here. » read more

Verifying Complex Chips
By Ed Sperling - 27 Feb, 2013 - Comments: 0

System-Level Design talks about what's changing in SoC verification with Janick Bergeron, verification fellow at Synopsys; Harry Foster, chief verification scientist at Mentor Graphics; Pranav Ashar, chief technology officer at Real Intent; Raik Brinkmann, president and CEO of OneSpin Solutions, and Tom Anderson, vice president of marketing at Breker Verification Systems. [youtube vid=DzDYyf... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 09 Feb, 2013 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

Mixing It Up
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

Managing Functional Verification Projects
By Various Writers - 31 Jan, 2013 - Comments: 0

The adoption of advanced verification languages and methodologies requires evolution of project management techniques in addition to the change in engineering practices. Managers must be able to assess and manage key project elements such as team expertise, verification methodology, verification IP (VIP) selection and environment setup to successfully deploy high-level verification environments... » read more

Adventures In Verification
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling Design complexity can be almost bit-mapped with verification complexity. There are so many things that need to be verified in a design these days that full coverage has become almost possible to guarantee. That has created a market for tools to help with the verification process—formal, functional, physical—and different methodologies for using those tools. But how to app... » read more

Experts At The Table: SoC Verification
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the challenges of verification with Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence; Charles Janac, chairman and CEO of Arteris, Venkat Iyer, CTO of Uniquify; and Adnan Hamid, CEO of Breker Verification Systems. What follows are excerpts of that discussion. SLD: Is the amount of time... » read more

Predictions, Problems And Prognosis
By Ed Sperling - 19 Dec, 2012 - Comments: 0

Never before in the long and often turbulent history of the semiconductor industry have so many problems presented themselves at each new process node. And never before have there been so many well-tested choices to resolving them. After possibly the most intensive, extensive and expensive research this industry has ever witnessed, Moore’s Law is now technologically assured down to at leas... » read more

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