tag: ANSYS

ANSYS 5G SoC Solutions
By Ansys - 10 Apr, 2019 - Comments: 0

System-On-Chips for 5G smartphones and networks are complicated since they need to manage huge amounts of antenna data and offer significantly high processing capabilities in a power and thermally constrained environments. ANSYS tools provide thermal, reliability, power-timing and electromagnetic analyses of SoCs that can reveal design weaknesses and prevent system failures. Multiphysics soluti... » read more

Blog Review: April 10
By Jesse Allen - 10 Apr, 2019 - Comments: 0

Arm's Paul Whatmough discusses the growing use of real-time computer vision on mobile devices and proposes transfer learning as a way to enable neural network workloads on resource-constrained hardware. Cadence's Anton Klotz highlights a collaboration with Imec and TU Eindhoven on cell-aware test that reduces defect simulation time by filtering out defects with equivalent fault effects. M... » read more

Big Shift In Multi-Core Design
By Ann Mutschler - 03 Apr, 2019 - Comments: 0

Hardware and software engineers have a long history of working independently of each other, but that insular behavior is changing in emerging areas such as AI, machine learning and automotive as the emphasis shifts to the system level. As these new markets consume more semiconductor content, they are having a big impact on the overall design process. The starting point in many of these desig... » read more

Digital Twins Deciphered
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

Utilizing More Data To Improve Chip Design
By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

Blog Review: Mar. 27
By Jesse Allen - 27 Mar, 2019 - Comments: 0

Rambus' Steven Woo takes a look at the memory requirements of neural networks and why some companies are using on-chip memory while others are using HBM2 or GDDR6. Cadence's Lana Chan  observes growing momentum for NVMe and highlights some new features in the latest specification that are pushing mainstream adoption forward. Mentor's Matthew Ballance contends that when it comes to adopti... » read more

Making Chip Packaging Simpler
By Ed Sperling and Mark LaPedus - 21 Mar, 2019 - Comments: 1

Packaging is emerging as one of the most critical elements in semiconductor design, but it's also proving difficult to master both technically and economically. The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing pr... » read more

Gaps In 5G Test
By Kevin Fogarty - 20 Mar, 2019 - Comments: 0

Add one more industry to the long list that analysts expect 5G technology to disrupt—test. While the initial versions of this wireless technology will be little more than a faster version of 4G, concern is growing about exactly how to test the second phase of this technology, which will be based upon millimeter wave. A number of fundamental problems need to be addressed. Among them: T... » read more

Blog Review: Mar. 20
By Jesse Allen - 20 Mar, 2019 - Comments: 0

Cadence's Paul McLellan argues that rapid improvements in the performance of general-purpose computing led to a lack of innovation in domain-specific architectures, but as scaling slows, they're entering a new golden age. In a video, Mentor's Colin Walls takes a look at the use of floating point in an embedded application and some of the pitfalls associated with it. Synopsys' Taylor Armer... » read more

Timing Is Of The Essence
By Ansys - 14 Mar, 2019 - Comments: 0

Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

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