tag: ANSYS

End-To-End Cell–Pack–System Solution: Rechargeable Lithium-Ion Battery
By Ansys - 08 May, 2019 - Comments: 0

Industry has become more interested in developing optimal energy storage systems as a result of increasing gasoline prices and environmental concerns. A major application for energy storage use is hybrid electric vehicles (HEVs) and electric vehicles (EVs). The rechargeable energy storage system is a key design issue, as it dominates overall vehicle performance. The system as a whole must deliv... » read more

Blog Review: May 8
By Jesse Allen - 08 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that the threat of cyber war on the financial system is a real possibility and points to four major vulnerability concerns. Cadence's Meera Collier takes a look at bees and technology, from smart hives to sensors that can be carried on the insects' backs. Mentor's Brent Klingforth argues that electrical and mechanic designers need to seamlessly share infor... » read more

Week In Review: Design, Low Power
By Jesse Allen - 03 May, 2019 - Comments: 0

ANSYS acquired the assets of DfR Solutions, a developer of automated design reliability analysis software. Founded in 2004 and based in Maryland, DfR's tool translates ECAD and MCAE data into 3D finite element models, automates thermal derating and performs thermal and mechanical analysis of electronics earlier in the design cycle. "ANSYS brings industry-leading electronic simulation capabiliti... » read more

Blog Review: May 1
By Jesse Allen - 01 May, 2019 - Comments: 0

Synopsys' Melissa Kirschner questions whether a unified standard for safety-related code development will be enough to secure connected cars as MISRA and AUTOSAR merge C++ guidelines. In a podcast, Mentor's Brent Klingforth and John McMillan share questions and answers about rigid-flex PCB design, including the value of incorporating flexible circuits and the key challenges faced when doing ... » read more

Focus Shifting From 2.5D To Fan-Outs For Lower Cost
By Ed Sperling - 29 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Moore’s Law Now Requires Advanced Packaging
By Ed Sperling - 18 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Blog Review: April 17
By Jesse Allen - 17 Apr, 2019 - Comments: 0

In a video, Mentor's Colin Walls digs into power management in embedded software with a particular look at the Power Pyramid model. Synopsys' Taylor Armerding checks out the state of application security at this year's RSA and finds that while organizations are paying attention to security through training and dedicated teams, roadblocks still remain. Cadence's Paul McLellan considers how... » read more

Low Power Meets Variability At 7/5nm
By Ann Mutschler - 11 Apr, 2019 - Comments: 0

Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

Multi-Physics At 5/3nm
By Ed Sperling - 11 Apr, 2019 - Comments: 0

Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

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