Safety, Security And PPA Tradeoffs


Safety and security are emerging as key design tradeoffs as chips are added into safety-critical markets, adding even more complexity into an already complicated optimization process. In the early days of semiconductor design, performance and area were traded off against each other. Then power became important, and the main tradeoffs became power, performance and area (PPA). But as chips inc... » read more

Blog Review: July 18


Synopsys' Shivani Bansal introduces DFI 5.0, the latest interface specification that defines signals, timing, and functionality required for efficient communication between the memory controller and PHY, including changes to boost performance in DDR5/LPDDR5. Mentor's Ricardo Anguiano contends that for greater autonomy in vehicles, centralized sensor fusion is necessary to both reduce the cos... » read more

5nm Design Progress


Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

In-Design Power Rail Analysis


Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

Fostering Thermal Design Innovation Using Chip-Package-System Analysis Techniques


As devices continue to become smaller and more portable Moore’s Law continues to increase the number of transistors that fit within a chip albeit many predict an end to this in the near future. However new interconnect technologies that use Through-Silicon-Vias (TSVs) can place ICs next to each other using 2.5D Interposers or stack chips in 3D resulting in even greater system scaling. This co... » read more

How To Test Autonomous Vehicles


By Kevin Fogarty and Ed Sperling The race is on to develop ways of testing autonomous vehicles to prove they are safe under most road conditions, but this has turned out to be much more difficult than initially thought. The autonomous vehicle technology itself is still in various stages of development, with carmakers struggling to fine-tune AI algorithms that can guide robots on wheels th... » read more

Preparing For A 5G World


Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Blog Review: July 11


Synopsys' Taylor Armerding warns that while significant router vulnerabilities have been known about for years, security mostly hasn't been getting better, leading to a 539% increase in attacks targeting routers since the fourth quarter of 2017. In a video, Mentor's Colin Walls walks through how to deal with the initialization of non-volatile RAM in embedded programming, including suggestion... » read more

Regulations Trail Autonomous Vehicles


Fragmented regulations and unrealistic expectations may be the biggest hurdles for chipmakers selling into the market for self-driving cars during the next few years. Carmakers and the semiconductor industry have made tremendous progress building real-time vision systems and artificial intelligence into relatively traditional automobiles during the past decade or so. But federal and state re... » read more

Week In Review: Design, Low Power


M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

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