tag: ANSYS

Turning Down The Power
By Jeff Dorsch - 11 Jan, 2018 - Comments: 0

Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

Performance Improvement By System Aware Substrate Noise Analysis For Mixed-signal IC
By Ansys - 10 Jan, 2018 - Comments: 0

The market wants mixed ICs that are smaller and cheaper, and even provide advanced features. To satisfy this contradiction, many mixed ICs makers are reducing their bill of materials (BOM) cost by decreasing the amount of materials in the package or on a board. But these cost-effective methods can cause significant performance degradation with intensified coupling effects due to substrate noise... » read more

Blog Review: Jan. 10
By Jesse Allen - 10 Jan, 2018 - Comments: 0

Rambus' Aharon Etengoff explains the Meltdown and Spectre CPU vulnerabilities and why they could negatively affect the semiconductor industry for decades. Cadence's Paul McLellan has an explainer on Meltdown and how it's an unintended consequence of a processor behaving as intended. Mentor's Ruben Ghulghazaryan and Jeff Wilson investigate using machine learning to predict post-deposition ... » read more

Blog Review: Jan. 3
By Jesse Allen - 03 Jan, 2018 - Comments: 0

Ansys' Steve Pytel argues that increased signaling speeds and frequencies have led to signal integrity issues that circuit simulation alone cannot handle. Cadence's Paul McLellan dives into the details of Intel's 10nm process, including three layers of self-aligned quadruple patterning, contact-over-active-gate, and cobalt for contact fill. Mentor's Ron Press and Vidya Neerkundar argue th... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2017 - Comments: 0

Mentor's Andrew Macleod points out five things that need to happen for autonomous and electric cars to move from R&D and test cases to mass-produced, commercially viable vehicles. Synopsys' Iain Singleton provides some tips on tackling large designs with formal and how the assume-guarantee technique helps split them without masking bugs. Cadence's Paul McLellan shares updates from the... » read more

Accounting For Power Earlier
By Ann Mutschler - 14 Dec, 2017 - Comments: 5

Concerns about power usage in an SoC are far from new, but the adoption of power management techniques still varies by company and by project. Leading semiconductor providers have made the necessary changes in tooling and methodology to account for [getkc id="106" kc_name="power awareness"] because they have to, but the rest of the industry hasn't necessarily caught up. “The companies t... » read more

EDA Challenges Machine Learning
By Brian Bailey - 14 Dec, 2017 - Comments: 1

Over the past few years, [getkc id="305" kc_name="machine learning"] (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. While there is clearly a lot of hype surrounding this, it appears that machine learning can produce a better outcome for many tasks in the EDA flow than even the... » read more

Blog Review: Dec. 13
By Jesse Allen - 13 Dec, 2017 - Comments: 0

Mentor's Sherif Hany notes that pattern matching isn't just for litho hotspots anymore, and is increasingly being used in a wide range of early design phase checks, DRC flows, layout retargeting and fixing and DFM checks. Synopsys' Eric Huang explains why USB cables have gotten so short, even though no length is mentioned in the specification. Cadence's Paul McLellan listens in as Jeremy ... » read more

CAE Turns To HPC
By Ansys - 13 Dec, 2017 - Comments: 0

How ANSYS is addressing the value of HPC technology within the CAE market, the main challenges to the use or uptake of HPC resources, and the future for HPC in CAE. The paper also briefly describes ANSYS Discovery Live — a new design tool that takes advantage of thousands of cores available in a GPU to produce instantaneous simulation results with every interactive change to the model. Discov... » read more

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