Digitalization: Best Practices For Designing Smart, Connected Products And Driving Business Outcomes


Today’s product designs contain more functionality per square inch than ever before. We’ve all been impacted by the growth of smartphones and other consumer products, but digitalization has impacted every industry, from manufacturing and transportation to health care. Even traditional products are being reimagined with new smart capabilities. In the current fast-paced, highly competitive gl... » read more

The Darker Side Of Machine Learning


Machine learning can be used for many purposes, but not all of them are good—or intentional. While much of the work underway is focused on the development of machine learning algorithms, how to train these systems and how to make them run faster and do more, there is a darker side to this technology. Some of that involves groups looking at what else machine learning can be used for. So... » read more

Blog Review: July 5


Cadence's Paul McLellan checks out the current state of System-in-Package technology and how different products incorporate SiP. Synopsys' Robert Vamosi digs into the differences between two major recent ransomware outbreaks, WanaCry and Petya. A Mentor staff writer shares some highlights from this year's DAC. ARM's Rene Haas examines what consumers think about AI and the impact it wil... » read more

Blog Review: June 28


Mentor's Craig Armenti notes the benefits, and challenges, of investing in modular design in the PCB domain. Cadence's Paul McLellan covers a DAC chat with CEO Lip-Bu Tan on the rise of advanced packaging and investments in AI and autonomous driving. Synopsys' Jim Hartnett examines some of the challenges and tradeoffs involved in building good security practices in hospital environments. ... » read more

The Week In Review: Design


M&A Silvaco will acquire SoC Solutions, adding more IP experience to the company's portfolio. SoC Solutions, based in Atlanta, GA, focuses on pre-configured IP subsystems and IP targeting low power IoT and machine-to-machine communication. Terms of the deal were not disclosed, but the acquisition is expected to close soon. Imagination is putting the rest of the company up for sale after... » read more

Tech Talk: 7nm Power


Annapoorna Krishnaswamy, lead applications engineer at ANSYS, talks with Semiconductor Engineering about power-related changes at 7nm and what engineering teams need to watch out for as they move down to the latest process technology. https://youtu.be/Ym46ssJPeHM » read more

Shrink Or Package?


Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

Modeling On-Chip Variation At 10/7nm


Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

Blog Review: June 14


In a video, Cadence's Tom Hackett looks at the evolving von Neumann computer architecture and the development of CCIX driven by recent cloud computing challenges. Mentor's Puneet Sinha notes it's been 17 years since the Toyota Prius went on sale worldwide, and looks ahead to the next 17 years of electric vehicles. Synopsys' Sri Deepti Pisipati gives an overview of the different topologies... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

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