tag: Arteris IP

Adding NoCs To FPGA SoCs
By Ann Mutschler - 28 Jun, 2018 - Comments: 0

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are facing some of the same issues as standard SoCs, including the ability to move larger and larger amounts of data quickly throughout an increasingly complex device, and the difficulty in verifying and de... » read more

Tuesday At DAC 2018
By Brian Bailey - 27 Jun, 2018 - Comments: 0

The morning starts with the Accellera Breakfast. Accellera has made some significant progress this year and we can expect to hear about the approval of the Portable Stimulus 1.0 specification later in the conference as well as the initial release of SystemC CCI as well as a proposal for the creation of an IP Security Assurance Working Group, which will discuss standards development to address s... » read more

The Week in Review: IoT
By Jeff Dorsch - 15 Jun, 2018 - Comments: 0

Tools/Chips Synopsys rolled out a new release of its automotive exterior lighting design and analysis software. The tool calculations and generates images for multiple viewing directions and different lighting conditions. Lighting on vehicles has become far more complex than just shining a beam on the road. The latest technology can adapt to road conditions, other cars, and help illuminate the... » read more

Chip Dis-Integration
By Brian Bailey - 14 Jun, 2018 - Comments: 2

Just because something can be done does not always mean that it should be done. One segment of the semiconductor industry is learning the hard way that continued chip integration has a significant downside. At the same time, another another group has just started to see the benefits of consolidating functionality onto a single substrate. Companies that have been following Moore's Law and hav... » read more

The Week In Review: Design
By Jesse Allen - 08 Jun, 2018 - Comments: 0

Tools & IP Synopsys added machine learning capabilities to its Design Platform. The company highlighted benefits to the PrimeTime signoff tool, which saw 5X faster power recovery in customer designs at leading-edge geometries. Renesas is using the tool, noting a 4X power ECO speed-up. ArterisIP unveiled a standalone last level cache (LLC) for high-performance SoCs. CodaCache can be adde... » read more

Tech Talk: ISO 26262 Drilldown
By Ed Sperling - 06 Jun, 2018 - Comments: 0

ArterisIP’s Kurt Shuler looks at what can go wrong in automotive design, what are the prerequisites for getting the attention of Tier 1 and OEMs, and what’s involved in automotive design at all levels. https://youtu.be/nnjAldn-nKU » read more

Progress And Chaos On Road To Autonomy
By Jeff Dorsch - 03 Jun, 2018 - Comments: 1

Progress in the development of fully autonomous vehicles is incremental and slow, but not for lack of effort. Research and development in self-driving cars is under way all around the globe, from the biggest automotive manufacturers and their Tier 1 suppliers to companies not traditionally involved in the automotive industry. Add to that fleets of startups working on sensor technologies and ... » read more

Analog Migration Equals Redesign
By Ann Mutschler - 24 May, 2018 - Comments: 1

Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes. In the finFET era, those challenges have only intensified for analog circuits. Reuse, fo... » read more

New Deep Learning Processors, Embedded FPGA Technologies, SoC Design Solutions
By Ty Garibay - 14 May, 2018 - Comments: 0

Some of the most valuable events at DAC are the IP Track sessions, which give small and midsize companies a chance to share innovations that might not get much attention elsewhere. The use of IP in SoCs has exploded in recent years. In a panel at DAC 2017, an industry expert noted that the IP market clearly was growing even faster than EDA itself, due to the fact that more and more chip mak... » read more

Power Optimization Strategies Widen
By Brian Bailey - 10 May, 2018 - Comments: 0

An increasing amount of electronic content in new and existing markets is creating different and sometimes competing demands for power optimization. For the past decade, EDA has been driven by the mobile phone industry, where the emphasis is on better power analysis and optimization tools to reduce power consumption and extend battery life. While energy efficiency continues to improve, other... » read more

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