tag: Arteris

Experts At The Table: Billion-Gate Design Challenges
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excer... » read more

Billion-Gate Chips
By Ed Sperling - 16 Mar, 2011 - Comments: 0

Low-Power Engineering examines hurdles ranging from power to cost in billion-gate IC designs with Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. [youtube vid=0jum2ThIVzg] » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 25 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is concurrent design strategic—meaning is it done at the architectural lev... » read more

Semiconductor M&A?
By Kurt Shuler - 24 Feb, 2011 - Comments: 0

Last week a friend of mine was giddy with joy as he exclaimed, “Semi M&A is back!” It seems Qualcomm’s acquisition of Atheros and Intel’s acquisition of Silicon Hive somehow changed the chemical makeup of his brain, transforming him from an eternal semiconductor market pessimist to a born-again optimist. Being someone who lives and dies by data, my initial response was, “Let’s s... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 18 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is there cross-training going on to allow for concurrent design? Brambilla... » read more

Concurrent Design
By Ed Sperling - 11 Feb, 2011 - Comments: 0

The idea of developing software and hardware simultaneously isn't new, but it has taken on renewed urgency in IC design because of growing complexity, including power and proximity issues. Low-Power Engineering captures the perspective of executives at four companies working in this market: Marco Brambilla of STMicroelectronics; Charlie Janac of Arteris; Mike Gianfagna of Atrenta, and Javier De... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 10 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: What is concurrent design and how has the definition changed? DeLaCruz: Th... » read more

The Quest To Better Define Applications
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ed Sperling For nearly five decades, just being able to get software to run on hardware and communicate with other systems was considered a feat of engineering. But with that part of the technology solved well enough, the next big challenge is to make sure that applications can run as efficiently as possible to maximize performance, minimize power consumption and limit the area required to ... » read more

Connecting System-Level Flows To Implementation Tools
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler With the complexity explosion occurring in SoC design today, there is a relentless force to push design decisions further up in terms of abstraction. Resolving issues at the gate level is not possible any more because there just isn’t enough time or resources. Further, the resulting design may not even be competitive because optimization at the gate level can leave ... » read more

Tailoring IP, Tools And Flows
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler As SoC and system complexity rises continually and software drives much more in a system, specific vertical application areas will require tailored IP and tool flows to allow designers to meet time-to-market demands. Today, many systems are designed around a platform, which contains most of the STAR IP—processors, GPUs, memory controllers, interconnects, memory s... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy