Unleashing Heterogeneous Compute: Lessons From Real-World System Design


At the Andes RISC-V CON Silicon Valley held in San Jose, California, in April 2025, Imagination Technologies and Baya Systems delivered a compelling presentation titled “Unleashing Heterogeneous Compute: Lessons from Real-World System Design.” This session, part of the developer track, showcased a joint demonstration leveraging Baya Systems’ WeaverPro CacheStudio software to model a... » read more

Government Funding For Chip Design Tools Spreads


Governments around the globe are starting to invest more heavily in chip design tools and related research as part of an effort to boost on-shore chip production, opening new opportunities for startups and established EDA companies. Those cash infusions, which are being doled out in the U.S., Europe, and Asia, are part of a growing recognition of the importance of design automation tools wit... » read more

Silicon Lifecycle Management Gains Traction, But It’s Complicated


Silicon lifecycle management (SLM) is gaining ground in semiconductor design and test by leveraging specialized on-die sensors and analytics engines to improve power, performance, yield, and reliability. Most modern SoCs mitigate the guesswork by leveraging DFT, which includes adding memory built-in self-test (BiST) or improving functional coverage, but these tests were meant for verifying c... » read more

A Quantum Leap in Architecture Design of Chiplet Cache Systems


CacheStudio is a rapid architecture and design platform for chiplet based cache coherent systems. Cache hierarchies and parameters are specified in minutes with an abstract Python front end, and accurate workload driven simulations are performed at millions of instructions per second to uncover stateful performance indicators that require long runtimes. The results are presented interacti... » read more

Best Options For Using AI In Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss how and where AI can be applied to chip design to maximize its value, and how that will impact the design process, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at S... » read more

Chip Industry Week in Review


Apple plans to increase its U.S. investment by an additional $100 billion over four years, which includes the launch of an advanced manufacturing supply chain program, spurring a number of related chip industry announcements, including: Apple will invest in Amkor's new packaging and test facility in Arizona as its first and largest customer, and Amkor will package and test Apple silicon pr... » read more

AI Drives More Realistic Gaming


Video games are utilizing artificial intelligence to create increasingly realistic scenarios and interactions, enabled by big increases in processing horsepower and memory, and significantly faster data movement. GPUs, once confined to graphics rendering, are now also being deployed across a wide range of AI tasks, generating more realistic non-player characters, dynamic worlds, personalized... » read more

For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency


Data centers and high-performance computing (HPC) are the primary enablers of today’s power-hungry AI-driven technology, but chip designers, EDA vendors, and the data centers themselves have a long list of options available to them to help curb AI's power consumption. Chip designers play a critical role in ensuring energy efficient processing from the bottom up, whether that is hardware-so... » read more

How AI Will Impact Chip Design And Designers


Experts at the Table: Semiconductor Engineering sat down to discuss the role and impact of AI in chip design with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir Arora, head of engineering... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow


As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

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