tag: Cadence

The Week In Review: Design
By Jesse Allen - 07 Apr, 2017 - Comments: 0

Name Changes Arteris changed its name to ArterisIP. The company said the name change better reflects what the company does, which is provide IP for SoC communication on-die and between die. Mentor Graphics also modified its name, following last week's announcement that the acquisition by Siemens has been completed. The company is now officially called Mentor, A Siemens Business. It also ... » read more

The Software Side Of Self-Driving
By Ann Mutschler - 06 Apr, 2017 - Comments: 0

Just as the overall system complexity is causing ripples through the automotive supply chain so too is managing the system complexity, with software in particular. With so much new technology, and so many new ideas to keep track of, it would seem a huge undertaking by the automotive OEMs. In the midst of making decisions about the usual incremental improvements, the system architecture decis... » read more

Self-Driving Cars Rattle Supply Chain
By Ann Mutschler - 06 Apr, 2017 - Comments: 0

Automotive compute workloads are consolidating as carmakers push toward autonomous vehicles, but the changes necessary to make this all work are causing huge disruptions in an industry that has fine-tuned its supply chain over more than a century. Consolidation is essential for a variety of reasons, including efficiency of the computations, complexity management, and lower deployment costs. ... » read more

Conflicting Goals In Data Centers
By Gale Morrison - 06 Apr, 2017 - Comments: 0

Two conflicting goals are emerging inside of data centers—speed at any cost, and the ability to extend hardware well beyond its expected lifetime to amortize that cost. Layered across both of those are concerns about how to move data back and forth more efficiently, how to secure it, and how to best integrate different generations of technology. But these widely different goals have create... » read more

Blog Review: April 5
By Jesse Allen - 05 Apr, 2017 - Comments: 0

In a video, Cadence's Megha Daga digs into the different architectural layers present in convolutional neural networks and how they contribute to object detection and classification in a real world scenario. Mentor's Mike Santarini argues that as things become increasingly connected, the stakes of bad design and bad verification are higher than they've ever been. Synopsys' Robert Vamosi w... » read more

The Great Machine Learning Race
By Ed Sperling - 03 Apr, 2017 - Comments: 2

Processor makers, tools vendors, and packaging houses are racing to position themselves for a role in machine learning, despite the fact that no one is quite sure which architecture is best for this technology or what ultimately will be successful. Rather than dampen investments, the uncertainty is fueling a frenzy. Money is pouring in from all sides. According to a new Moor Insights report,... » read more

HBM Upstages DDR In Bandwidth, Power
By Ann Mutschler - 30 Mar, 2017 - Comments: 1

For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

Blog Review: March 29
By Jesse Allen - 29 Mar, 2017 - Comments: 0

In a video, Cadence's Megha Daga introduces how convolutional neural networks identify objects and the wide range of applications for the technology. Mentor's Ron Press proposes a way to take advantage of hierarchical DFT features, even if a design wasn't designed for it. Synopsys' Robert Vamosi shares highlights of the RAND Corporation's extensive report examining zero day vulnerabilitie... » read more

Supporting CPUs Plus FPGAs (Part 1)
By Brian Bailey - 27 Mar, 2017 - Comments: 3

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

The Week In Review: Design
By Jesse Allen - 24 Mar, 2017 - Comments: 0

Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

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