tag: Cadence

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 17 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low power products at [getentity id="22032" ... » read more

Blog Review: Aug. 17
By Jesse Allen - 17 Aug, 2016 - Comments: 0

Mentor's Andrew Macleod listens in on the most pressing electrical engineering and embedded software challenges in the automotive industry today, in an IESF presentation by Paul Johnston. Many flash memory protocols have appeared, and Synopsys' Rahul Ramesh Chaudhari delves into ONFi in particular. Cadence's Paul McLellan digs into the challenges facing the development and roll out of 5G.... » read more

New Architectures, Approaches To Speed Up Chips
By Ed Sperling - 15 Aug, 2016 - Comments: 2

The need for speed is back. An explosion in the amount of data that needs to be collected and processed is driving a new wave of change in hardware, software and overall system design. After years of emphasizing power reduction, performance has re-emerged as a top concern in a variety of applications such as smarter cars, wearable devices and cloud data centers. But how to get there has cha... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

The Role Of Energy-Efficient Circuits In Wearable Healthcare Applications
By Christine Young - 11 Aug, 2016 - Comments: 0

As beneficial as they are, health monitors for conditions like high blood pressure, arrhythmia, and epilepsy can be uncomfortable and inconvenient due to all of their protruding wires. This opens up an opportunity for designers of wearable healthcare applications. “Wearable electronics are needed for proactive healthcare,” said Dr. Jerald Yoo, an associate professor in the Department of ... » read more

Does Power Analysis Need To Be Accurate?
By Ann Mutschler - 11 Aug, 2016 - Comments: 1

The mere mention of accuracy in power analysis and optimization today can trigger a contentious discussion, even among typically reserved engineers. What is needed and where? Which tools are truly as accurate as claimed? And how much accuracy is actually needed for power analysis, [getkc id="112" kc_name="estimation"], and optimization? First of all, the accuracy required really depends o... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

Reaching The Power Budget
By Ann Mutschler - 11 Aug, 2016 - Comments: 1

Everything related to power in chip design today is a big deal—and it’s just getting bigger. Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

Accelerating Monte Carlo Analysis At Advanced Nodes
By Cadence - 10 Aug, 2016 - Comments: 0

Advanced-node designs have much larger variation, making it much more difficult to achieve high yields at these processes. But can you really afford to run thousands or even millions of statistical simulations to predict how well your design will meet its specs? Or overdesign to accommodate manufacturing variations? In this paper, we will introduce a fast Monte Carlo analysis technique that del... » read more

Blog Review: Aug. 10
By Jesse Allen - 10 Aug, 2016 - Comments: 0

Is the end near for FinFETs? Applied's Mike Chudzik digs into the impact of rising parasitic resistance and parasitic capacitance and the challenges of scaling to 5nm. Cadence's Paul McLellan checks out the method UC Berkeley is using to build RISC-V processors. Mentor's Colin Walls warns that in C even the simplest things, like the declaration of variables, have pitfalls for the unwary. ... » read more

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