tag: Cadence

Blog Review: Sept. 24
By Ed Sperling - 24 Sep, 2014 - Comments: 0

Cadence’s Brian Fuller captures Chris Rowen’s phylum classifications for data-efficient design—lots of insects and much bigger but fewer mammals. There are cognitive layers in between, as well. Check out the chart. Mentor’s Robin Bornoff digs into thermal runaway and how to determine when it will occur—and burn up a chip. There’s a video to illustrate just what can go wrong. ... » read more

Executive Insight: Lip-Bu Tan
By Ed Sperling - 22 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down with [getperson id="11693" comment="Lip-Bu Tan"], president and CEO of [getentity id="22032" e_name ="Cadence"], to discuss his outlook on EDA, Moore’s Law and his strategy for investing in startups around the world. What follows are excerpts of that conversation. SE: What’s worrying you these days? Tan: There are a couple of things. One is the complex... » read more

EDA Vendors Prepare For 7nm
By Ann Mutschler - 18 Sep, 2014 - Comments: 0

It’s not too early to begin looking at design tools for the 7nm, even though the node is not expected to be production-ready until later this decade. While still in the early stages, foundries already in development with leading EDA companies, even though the water remains murky at this point. “7nm right now is in early definition, so we don't know exactly what it will be,” observed... » read more

Blog Review: Sept. 17
By Ed Sperling - 17 Sep, 2014 - Comments: 0

Ansys’ Benoit Debbaut looks at the Pitch drop experiment, which was started in 1927 (yes, that date is correct) to observe the excruciatingly slow movement of a thick liquid weighted down by gravity. Since inception, a total of nine drops have fallen. So when will the tenth drop fall? Place your bets...when you get around to it. Mentor’s Matthew Ballance highlights an interesting challe... » read more

More Than Moore
By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

How Reliable Is Your IP?
By Ed Sperling - 12 Sep, 2014 - Comments: 0

Almost everyone who has bought a new smartphone, car, home electronics device or appliance either has experienced technical glitches that require a replacement or repair, or they know someone who has experienced these problems. The good news is that only a very small fraction of the electronic glitches or failures can be contributed to hardware design. Most of it is due to manufacturing vari... » read more

Making Chips Run Faster
By Ed Sperling - 11 Sep, 2014 - Comments: 3

For all the talk about low power, the real focus of most chipmakers is still performance. The reality is that OEMs might be willing to sacrifice increasing performance for longer battery life, but they will rarely lower performance to reach that goal. This is more obvious for some applications than others. A machine monitor probably isn’t the place where performance will make much of a dif... » read more

Limiters To The Internet Of Things
By Brian Bailey - 11 Sep, 2014 - Comments: 0

“Specialization is for insects.” Robert A. Heinlein, Time Enough for Love In many respects, the [getkc id="76" kc_name="Internet of Things"] (IoT) is already here. But because most of it is not directed at the consumer space, it seamlessly blends into the environment, unnoticed by everyone except for those who are reaping the benefits of it. When we talk about the IoT, most people concentr... » read more

Design For IoT
By Ann Mutschler - 11 Sep, 2014 - Comments: 0

In our already mind-bogglingly connected world where you can control your BMW with a Samsung smartwatch or monitor and pay your parking meter with a credit card on your smartphone, the semiconductor design community is mulling over the opportunities from design kits to embedded software as far as the best ways to equip design teams for the [getkc id="76" comment="Internet of Things"] (IoT) era.... » read more

Are We Headed For A Power Wall?
By Ann Mutschler - 11 Sep, 2014 - Comments: 0

A common theme in semiconductor design circles today are the many power reduction techniques available to engineers to bring the power down in their devices. While power gating and other techniques are effective today, it does lead to questions about how long they will continue providing a benefit. Anand Iyer, director of product marketing for [getentity id="22016" e_name="Calypto"], believe... » read more

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