tag: Cadence

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

The Week In Review: May 31
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification pl... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design... » read more

The X Factor
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market windows. Tools are available to deal with some of these unknowns, or X’s, but certainly not all of them. Moreover, no single tool can handle all unknowns, some of which can build upon other unkn... » read more

The Growing Need For Behavioral Modeling
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to behavioral or functional modeling, there is an inherent notion of function, architecture and interconnect. This approach has long been considered a future requirement, but in complex designs the future part no longer applies. Behavioral modeling is a way of isolating or abstracting out a key part of the architectural description and making sure i... » read more

Pitfalls In Subsystem Reuse
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Experts At The Table: The Internet Of Everything
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the Internet of Things with Jack Guedj, president and CEO of Tensilica; John Heinlein, vice president of marketing for the physical IP division of ARM; Kamran Izadi, director of sourcing and supplier management at Cisco; and Oleg Logvinov, director of market development for STMicroelectronics’ Industrial and Power Conversion Division. Wh... » read more

Experience Required
By The SE Staff - 30 May, 2013 - Comments: 0

Many prominent semiconductor, EDA and IP companies are acknowledging the influence of user-experience design methodologies and technologies on their business. Experiences are the evolution of commoditization (chip hardware) and customization (software). But many design engineers remain cautious about the actual application of experiences to their work. What is driving this emphasis on expe... » read more

Software-Driven Electronic Design Automation
By Frank Schirrmeister - 21 May, 2013 - Comments: 1

As the EDA industry prepares to descend on Austin in less than two weeks for the 50th annual Design Automation Conference (DAC), I am wondering what this DAC will be about. It’s pretty simple. One of the key themes will be about “software-driven EDA,” a term I’d love to claim to have invented but am happy to attribute to Jim Ready of Ready Systems and Montavista fame – our chief techn... » read more

3D Brings Test Into Fashion
By Ann Mutschler - 16 May, 2013 - Comments: 0

By Ann Steffora Mutschler As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to... » read more

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