Solving Clock Signal Integrity And Jitter Issues


A recent blog post discussed the challenges of clock signal integrity and clock jitter in deep submicron semiconductor devices. Nice, clean clock signals are degraded due to many factors, including noise in the power delivery network (PDN). Timing variation due to clock jitter is also a serious issue, especially for chips operating at low voltage with high frequencies. The impact due to cloc... » read more

The Design Challenges Of Clock Integrity And Clock Jitter


Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal integrity and introduce jitter include thermal effects, manufacturing flaws, signal crosstalk, IR (voltage) drop, signal loss over long runs, reflections, electromagnetic interference (EMI), ground bounc... » read more