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IP Integration Verification At DVClub Europe


Most people involved in pre-silicon verification of digital designs and electronic design automation (EDA) know the folks at Test and Verification Solutions (T&VS – now acquired by Tessolve to offer a full VLSI and test service). Among other things, they organize the Verification Futures (VF) conference in the UK and the DVClub Europe meetings. These are highly technical events, with plen... » read more

Scaling Formal Connectivity Checking To Multi-Billion-Gate SoCs With Specification Automation


Connectivity checking is a popular formal verification application. Formal tools can automatically generate assertions using a specification table as input and prove them exhaustively. Simulation-based verification, on the other hand, requires significantly more effort while providing a fraction of the coverage. However, chip complexity is rapidly increasing. ASICs and FPGAs for heterogeneous c... » read more

Connectivity Checking Is A Perfect Fit For Formal Verification


Formal verification has traditionally been regarded as an advanced technique for experts to thoroughly verify individual blocks of logic, or perhaps small clusters of blocks. However, if you talk to anyone involved in the field these days, you’ll find that the majority of formal users are running applications (“apps”) targeted for specific verification problems. Further, many of these app... » read more