Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)


A new technical paper titled "OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs" was published by researchers at Georgia Institute of Technology. Abstract "High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential language like ... » read more