What’s Next For Transistors And Chiplets

By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Device Performance

By Coventor - 15 Sep, 2021 - Comments: 1

In this paper, a 5nm FinFET flow was built using the SEMulator3D virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated usi... » read more

Angstrom-Level Measurements With AFMs

By Mark LaPedus - 19 Aug, 2021 - Comments: 0

Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

Stacked Nanosheets And Forksheet FETs

By Katherine Derbyshire - 19 Aug, 2021 - Comments: 0

What comes next after gate-all-around FETs is still being worked out, but it likely will involve some version of stacked nanosheets. The design of advanced transistors is a tradeoff. On one hand, it takes less gate capacitance to control a thin channel. On the other hand, thin channels can’t carry as much drive current. Stacked nanosheet designs seek to reconcile these two objectives by... » read more

Using A Virtual DOE To Predict Process Windows And Device Performance Of Advanced FinFET Technology

By Qingpeng Wang - 03 Aug, 2021 - Comments: 0

By Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang, and Joseph Ervin Introduction With continuing finFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch rate on a wafer is dependent upon existing feature sizes and local pattern density. Uninten... » read more

MEMS: New Materials, Markets And Packaging

By Ed Sperling - 28 Jul, 2021 - Comments: 1

Semiconductor Engineering sat down to talk about future developments and challenges for microelectromechanical systems (MEMS) with Gerold Schropfer, director of MEMS products and European operations in Lam Research's Computational Products group, and Michelle Bourke, senior director of strategic marketing for Lam's Customer Support Business Group. What follows are excerpts of that conversation.... » read more

Using Virtual Process Libraries To Improve Semiconductor Manufacturing

By Jeonghoon (James) Kim - 17 Jun, 2021 - Comments: 0

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where researchers are trying to develop a systematic approach to understanding a process mechanism. However, it is definitely not true in production fabs, where engineers need to quickly a... » read more

Expanded Material Metrology For Refined Etch Selectivities

By Anoop Somanchi - 08 Jun, 2021 - Comments: 0

Trends in advanced device fabrication require combined lithography-etching multi-patterning sequences and self-aligned multi-patterning to form devices’ finest features at subwavelength dimensions. As EUV lithography (13.5 nm) progresses to larger numerical apertures and new thin resists, new multipatterning sequences must be developed with mutually compatible resists and proximal layers t... » read more

Demand, Lead Times Soar For 300mm Equipment

By Mark LaPedus - 20 May, 2021 - Comments: 0

A surge in demand for various chips is causing select shortages and extended lead times for many types of 300mm semiconductor equipment, photomask tools, wafers, and other products. For the last several years, 200mm equipment has been in short supply in the market, but issues are now cropping up throughout the 300mm supply chain, as well. Traditionally, lead times have been three to six mont... » read more

What’s Next In Fab Tool Technologies?

By Mark LaPedus - 12 May, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and other next-generation fab technologies with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fuj... » read more

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tag: etch

What’s Next For Transistors And Chiplets

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Device Performance

Angstrom-Level Measurements With AFMs

Stacked Nanosheets And Forksheet FETs

Using A Virtual DOE To Predict Process Windows And Device Performance Of Advanced FinFET Technology

MEMS: New Materials, Markets And Packaging

Using Virtual Process Libraries To Improve Semiconductor Manufacturing

Expanded Material Metrology For Refined Etch Selectivities

Demand, Lead Times Soar For 300mm Equipment

What’s Next In Fab Tool Technologies?

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