tag: Eureka

Startup Funding: Q1 2026

By Jesse Allen - 13 Apr, 2026 - Comments: 0

The new year started off with a bang for private semiconductor companies, with 18 garnering mega funding rounds exceeding $100 million, and two, Rapidus and Cerebras, reaching the $1 billion mark. Predictably, the vast majority of those are either designing chips primarily for AI inference workloads or attempting to overcome bandwidth limitations by improving interconnects from the chip level t... » read more

Startup Funding: January 2024

By Jesse Allen - 07 Feb, 2024 - Comments: 0

Big rounds marked January, with three companies raising over $100 million. Quantum computing topped the list, with the company that resulted from the merger of Cambridge Quantum Computing and Honeywell's quantum division raking in the third-largest round for a quantum computing company ever. Another chart-topper was an advanced packaging company that began mass production in its first factor... » read more

Trending Articles

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

Flash Getting Stacked High-Bandwidth Version

Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.

AI Accelerator Testing Depends On DFT Innovations

Multi-die assemblies greatly increase the number of things that can go wrong, and the difficulty of finding them.

by Laura Peters

Chiplets Need A New Workflow

Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.

by Ann Mutschler

HBM Shifts Testing Left To Preserve AI Chip Yield

Testing sooner and more often can improve quality and reduce scrap, but it's also more costly.

by Anne Meixner

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Can A Computer Science Student Be Taught To Design Hardware?

To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.

by Liz Allan

Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate

Making Hybrid Bonding Better

Why this technology is so essential for multi-die assemblies, and how it can be improved.

by Laura Peters

When Semiconductor Materials Misbehave

The gap between lab performance and fab reality is growing wider as packages grow more complex.

by Gregory Haley

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.

by Laura Peters

Silicon Photonics In The Data Center: What A CMOS Exec Needs To Know

Photonics will replace copper for all interconnects in ~5 years; TSMC may go from zero to #1

by Geoff Tate

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