Co-Designing Data Center Architecture To Support LLMs (Intel, Georgia Tech)


A new technical paper titled "Scaling Intelligence: Designing Data Centers for Next-Gen Language Models" was published by Intel Corporation and Georgia Tech. An excerpt from the paper's abstract: "Our work provides a comprehensive co-design framework that jointly explores FLOPS, HBM bandwidth and capacity, multiple network topologies (two-tier vs. FullFlat optical), the size of the scale-ou... » read more

Tech Talk: On-Chip Variation


Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more