Chip Industry Week In Review

By The SE Staff - 15 Sep, 2023 - Comments: 0

By Gregory Haley, Jesse Allen, and Liz Allan TSMC told equipment vendors to delay deliveries of the most advanced tools due to uncertain demand, according to Reuters. The news drove down stock prices of all the major equipment providers. On the other hand, TSMC said advanced packaging shortages will constrain AI chip shipments for the next 18 months, according to NikkeiAsia. The United St... » read more

Week In Review: Manufacturing, Test

By Karen Heyman - 25 Aug, 2023 - Comments: 0

Intel aims to quadruple capacity for its most advanced chip packaging services by 2025, including with a new facility in Malaysia, per Nikkei Asia. Huawei is building a collection of secret semiconductor fabrication facilities across China to let the company skirt U.S. sanctions, SIA warned in a presentation seen by Bloomberg. It’s acquired at least two existing plants and is building at l... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 28 May, 2021 - Comments: 0

Pervasive computing — IoT, edge, cloud, data center, and back Cadence announced it has found a cost-conscience way to scale capacity for 3D electromagnetic (EM) simulations using a hybrid cloud consisting of local computing resources and cloud services from Amazon Web Service (AWS). Data stays safe on the local resources, and, if more computing resources are needed, encrypted simulation-spec... » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

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Chip Industry Week In Review

Week In Review: Manufacturing, Test

Week In Review: Auto, Security, Pervasive Computing

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