tag: Lam Research

Improving Reliability For GaN And SiC
By Mark LaPedus - 18 Jun, 2020 - Comments: 2

Suppliers of gallium nitride (GaN) and silicon carbide (SiC) power devices are rolling out the next wave of products with some new and impressive specs. But before these devices are incorporated in systems, they must prove to be reliable. As with previous products, suppliers are quick to point out that the new devices are reliable, although there are some issues that can occasionally surface... » read more

Using Fab Sensors To Reduce Auto Defects
By Anne Meixner - 09 Jun, 2020 - Comments: 0

The semiconductor manufacturing ecosystem has begun collaborating on ways to effectively use wafer data to meet the stringent quality and reliability requirements for automotive ICs. Silicon manufacturing companies are now leveraging equipment and inspection monitors to proactively identify impactful defects prior to electrical test. Using machine learning techniques, they combine the monitor ... » read more

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)
By Benjamin Vincent - 01 Jun, 2020 - Comments: 0

In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we r... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options Done By Virtual Fabrication
By Coventor - 01 Jun, 2020 - Comments: 0

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanoshe... » read more

EUV’s Uncertain Future At 3nm And Below
By Mark LaPedus - 21 May, 2020 - Comments: 5

Several foundries have moved extreme ultraviolet (EUV) lithography into production at both 7nm and 5nm, but now the industry is preparing for the next phase of the technology at 3nm and beyond. In R&D, the industry is developing new EUV scanners, masks and resists for the next nodes. 3nm is slated for 2022, followed by 2nm a year or two later. Nonetheless, it will require massive funding... » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

Fan-Out Wafer-Level Packaging And Copper Electrodeposition
By Steven T. Mayer - 21 May, 2020 - Comments: 0

By Steven T. Mayer, Bryan Buckalew, and Kari Thorkelsson As integrated circuit designers bring more sophisticated chip functionality into smaller spaces, heterogeneous integration, including 3D stacking of devices, becomes an increasingly useful and cost-effective way of mixing and connecting various functional technologies. One of the heterogeneous integration platforms gaining increased ac... » read more

New Uses For Manufacturing Data
By Ed Sperling - 12 May, 2020 - Comments: 0

The semiconductor industry is becoming more reliant on data analytics to ensure that a chip will work as expected over its projected lifetime, but that data is frequently inconsistent or incomplete, and some of the most useful data is being hoarded by companies for competitive reasons. The volume of data is rising at each new process node, where there are simply more things to keep track of,... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 24 Apr, 2020 - Comments: 0

Chipmakers Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. There are already signs that the foundries have pushed out their 3nm production schedules. So, expect 7nm and 5nm to become long-running nodes. At 3nm, Samsung and TSMC are going in different directions. Samsung is developing a gate-all-around (GAA) technology called nanosheet FETs. TSMC will e... » read more

Identifying And Preventing Process Failures At 7nm
By Qingpeng Wang - 20 Apr, 2020 - Comments: 0

Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, particularly at advanced nodes with smaller feature sizes. Traditionally, cross-correlation and analysis of thousands of test data points have been required to identify and prevent process failures. This is very costly in terms of both time and money. Fortunately, semiconductor virtual fab... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy