Flexible AI-MCU For Fast Inference of Transformer Models At The Ultra-Low-Power Edge (ETH Zurich, U. Bologna)


Researchers from ETH Zurich and University of Bologna have released “CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees”. Abstract “We present Chimera, a flexible and scalable Microcontroller Unit (MCU) designed to accelerate real-time inference of rapidly evolving transformer-based models a... » read more

Multi-DRAM Memory Subsystems In SoCs


Even with DRAM capacity going up with each generation of DRAM, the demand for memory densities by a variety of applications is growing at an even faster rate. To support these high memory densities and bus width requirements (that are typically more than what a single DRAM can support), almost all the new generation of memory subsystems and SoCs have multiple DRAM dies combined to effectively c... » read more

Memory Subsystems In Edge Inferencing Chips


Geoff Tate, CEO of Flex Logix, talks about key issues in a memory subsystem in an inferencing chip, how factors like heat can affect performance, and where these kinds of chips will be used. » read more