tag: Mentor

Have It All With No-Compromise DFT
By Geir Eide - 28 Jan, 2021 - Comments: 0

The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels. The pin-multiplexing (mux) approach works fine for smaller designs but can become problematic with an increase in the number of cores and the design complexity on today’s SoCs. The next revol... » read more

Roaring ’20s For The Chip Industry
By Brian Bailey - 28 Jan, 2021 - Comments: 0

2020 was a good year for the semiconductor industry and the EDA industry that fuels it, but 2021 has the opportunity to be even better. New end application markets continue to open, and what were once seen as technical hurdles are leading to a multitude of innovative solutions, all of which need suitable tooling. No company can afford to invest everywhere, and so for EDA companies, their rel... » read more

Big Changes In Verification
By Ann Mutschler - 28 Jan, 2021 - Comments: 0

Verification is undergoing fundamental change as chips become increasingly complex, heterogeneous, and integrated into larger systems. Tools, methodologies, and the mindset of verification engineers themselves are all shifting to adapt to these new designs, although with so many moving pieces this isn't always so easy to comprehend. Ferreting out bugs in a design now requires a multi-faceted... » read more

Taming Non-Predictable Systems
By Brian Bailey - 28 Jan, 2021 - Comments: 0

How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision makers invariably decide that some degree of uncertainty is warranted. Understanding uncertainty is at least the first step to making informed decisions, but new tooling is required to assess the im... » read more

Streaming Scan Network
By Siemens EDA - 27 Jan, 2021 - Comments: 0

The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT alleviates some of those challenges, by itself, is no longer enough. Adding Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-lev... » read more

Blog Review: Jan. 27
By Jesse Allen - 27 Jan, 2021 - Comments: 0

Synopsys' Godwin Maben finds that applications like high-performance computing and AI are bringing new dynamics to the power equation, and the key power considerations for chip design that will likely emerge over the course of the year. Siemens EDA's Harry Foster checks out trends in verification technology adoption for IC and ASIC design, with increasing numbers of designs using both dynami... » read more

The Good, Bad And Unknowns Of Flexible Devices
By Ed Sperling - 27 Jan, 2021 - Comments: 0

Flexible hybrid electronics are beginning to proliferate in consumer, medical, and industrial applications due to their comparatively low weight, thin profile, and the ability to literally bend the rules of design. Open any smart phone today and you're likely to find one or more of these flexible boards. Unlike standard printed circuit boards, FHE devices are printed using a combination of r... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Jan, 2021 - Comments: 0

Cadence will acquire NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. “Next-generation products and systems require comprehensive multi-physics engineering solutions encompassing IP, semiconductors, IC packaging, modules, board... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 22 Jan, 2021 - Comments: 0

Automotive/Mobility Former U.S. president Donald Trump pardoned the former Google engineer who plead guilty to taking Google’s self-driving car trade secrets before becoming the head of Uber Technologies’ self-driving car unit. Anthony Levandowski was sentenced 18 months in prison in August after pleading guilty in March to one count of a 33-charge indictment, according to a story in Reute... » read more

Blog Review: Jan. 20
By Jesse Allen - 20 Jan, 2021 - Comments: 0

Siemens EDA's Harry Foster takes a look at the amount of time IC and ASIC projects spend in verification, changes in the number of engineers on a project, and how engineers are spending their time. Synopsys' Stelios Diamantidis considers the importance of specialized accelerators for AI workloads as both cloud and edge push the PPA limits of current technologies. Cadence's Paul McLellan p... » read more

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