tag: Mentor

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 07 Aug, 2020 - Comments: 0

Pervasive computing — data center, edge, IoT Codasip and Metrics Design Automation announced they have integrated Metrics’ SystemVerilog RTL Simulation Platform within Codasip’s SweRV Core Support Package, version, and it will be accessible on the cloud. Aldec’s TySOM Embedded Development Kits have qualified for Amazon Web Services (AWS) IoT Greengrass. TySOM is a family of Xilinx Z... » read more

Best Practices And Constraint Management Tools Speed RF Design For The IoT
By Jim Martens - 06 Aug, 2020 - Comments: 0

By Jim Martens and David Zima The IoT has increased the demand for good radio frequency (RF) design practices from the mains, to wall outlet power, all the way to the antenna. With several IoT standards employed today, constraint management has become critical to ensuring that designs meet product performance and reliability. Even the simplest of IoT designs can benefit from constraint ma... » read more

Virtualization In The Car
By Ann Mutschler - 06 Aug, 2020 - Comments: 1

As the automotive industry grapples with complexity due to electrification and increasing autonomy of vehicles, consolidation of ECUs within vehicles, more stringent safety and security requirements, automotive ecosystem players are looking to virtualization concepts in a number of ways to realize the vehicles of tomorrow. One way is with hardware virtualization; the ability of a device such... » read more

Re-Imagining Electrical System Design
By Mentor, a Siemens Business - 05 Aug, 2020 - Comments: 0

Electrical system complexity is reaching a tipping point across industries, from modern passenger vehicles to sophisticated industrial machines that can now contain nearly 5,000 wiring harnesses. The electrical systems of these machines contain multiple networks, thousands of sensors and actuators, miles of wiring and tens of thousands of discrete components. Designing these complex systems is ... » read more

Blog Review: Aug. 5
By Jesse Allen - 05 Aug, 2020 - Comments: 0

Rambus' Scott Best explains some more sophisticated chip attacks, such as side-channel attacks, clocking attacks, fault injection, and infrared emission analysis, and countermeasures that can be adopted against them. Arm's Mark O'Connor considers ways that deployed neural networks could adapt to examples it sees in real-world use and generate more accurate predictions. Mentor's Chris Spea... » read more

Problems And Solutions In Analog Design
By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

Creating Better Models For Software And Hardware Verification
By Ed Sperling - 04 Aug, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Pivoting Toward Safety-Critical Verification In Cars
By Ann Mutschler - 31 Jul, 2020 - Comments: 1

The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Universal Verification Methodology Running Out Of Steam
By Ann Mutschler - 30 Jul, 2020 - Comments: 2

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

Open-Source Verification
By Brian Bailey - 30 Jul, 2020 - Comments: 1

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

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