tag: Mentor

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Power Is Limiting Machine Learning Deployments
By Brian Bailey - 25 Jul, 2019 - Comments: 3

The total amount of power consumed for machine learning tasks is staggering. Until a few years ago we did not have computers powerful enough to run many of the algorithms, but the repurposing of the GPU gave the industry the horsepower that it needed. The problem is that the GPU is not well suited to the task, and most of the power consumed is waste. While machine learning has provided many ... » read more

Taking EDA To The Cloud
By Omar El-Sewefy - 25 Jul, 2019 - Comments: 0

By now, virtually everyone knows about the “cloud”—that amorphous delivery of computing services over the Internet. Servers, storage, databases, networking, software, analytics, intelligence, and more are all on offer. Clouds may be private and limited to a single organization (enterprise clouds), be available to many organizations (public cloud), or a combination of both (hybrid cloud). ... » read more

Hybrid Emulation Takes Center Stage
By Ann Mutschler - 25 Jul, 2019 - Comments: 0

From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator. For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verific... » read more

Konica Minolta Proves C++ Level Signoff Possibilities Using Catapult HLS Platform
By Mentor, a Siemens Business - 24 Jul, 2019 - Comments: 0

A team’s ultimate goal is to move verification up to the C++ level in order to minimize the time spent in RTL verification and to achieve C++ signoff. A team at Konica Minolta® has been using the Catapult HLS Platform for many years to dramatically improve their productivity by coding at the C++ level and using the platform to generate RTL. They recently evaluated the high-level verification... » read more

Cybersecurity And Functional Safety: The Case For Embedded Analytics
By UltraSoC - 24 Jul, 2019 - Comments: 0

From advanced driver assistance systems (ADAS) to a new generation of robots and medical systems, we are seeing an explosion in the development of cyber-physical systems. Because these systems use advanced software to interact with the physical world, security and safety are paramount concerns. These issues are reflected in many industries by the use of safety and security standards based on a ... » read more

Blog Review: July 24
By Jesse Allen - 24 Jul, 2019 - Comments: 0

Synopsys' Taylor Armerding notes that while two Florida cities may have saved taxpayers millions by paying ransomware demands, doing so is likely setting up a ransomware tsunami that threatens other municipalities. In a video, Cadence's Jacek Duda digs into what's going on with the upcoming USB4 standard and what will change compared to USB 3.x. Mentor's Colin Walls shares a few embedded ... » read more

Using Memory Differently To Boost Speed
By Ed Sperling - 22 Jul, 2019 - Comments: 2

Boosting memory performance to handle a rising flood of data is driving chipmakers to explore new memory types and different ways of using existing memory, but it also is creating some complex new challenges. For most of the semiconductor design industry, memory has been a non-issue for the past couple of decades. The main concerns were price and size, but memory makers have been more than a... » read more

Partitioning Drives Architectural Considerations
By Ann Mutschler - 19 Jul, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

Blog Review: July 17
By Jesse Allen - 17 Jul, 2019 - Comments: 0

Mentor's John McMillan takes a look at the three general classes that have been established by IPC-2221B to reflect progressive increases in sophistication, functional performance requirements, and testing/inspection frequency for PCBs. Synopsys' Dinesh Siwal and Thenmozhy Kaliyamurthy point out the new features and improvements in DisplayPort 2.0, including greater speeds, better power effi... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy