Timing Leaks In Embedded MIPS Processors (Rochester)


Researchers from Rochester Institute of Technology published a technical paper titled “MIPSBLEED: Uncovering Microarchitectural Timing Leaks in Pervasive Embedded Processors.” Excerpt from abstract "This paper exposes how Simultaneous Multithreading (SMT), a feature increasingly used to boost performance in these environments, creates powerful cross-core timing channels on MIPS-based ... » read more

Microarchitectural Side-Channel Attacks and Mitigations on the On-Chip Mesh Interconnect


This new technical paper titled "Don't Mesh Around: Side-Channel Attacks and Mitigations on Mesh Interconnects" was presented by researchers at University of Illinois at Urbana-Champaign, MIT, and Texas Advanced Computing Center at the USENIX Security Symposium in Boston in August 2022. Abstract: "This paper studies microarchitectural side-channel attacks and mitigations on the on-chip mes... » read more