tag: Netherlands Forensic Institute

Chip Industry Week in Review

By The SE Staff - 12 Dec, 2025 - Comments: 0

Deals of the week: Arteris announced plans to acquire cybersecurity provider Cycuity. “Expanding our technology portfolio to include Cycuity’s hardware security assurance products will enable our customers to achieve secure on-chip data movement,” said Charlie Janac, chairman and CEO of Arteris. Qualcomm acquired Ventana Micro Systems, a maker of RISC-V data center-class CPU IP. ... » read more

Week In Review: Auto, Security, Pervasive Computing

By Ed Sperling - 22 Oct, 2021 - Comments: 0

An investigation by the Automobile Association of America found that lane-keeping assist and automatic emergency braking, both high-profile ADAS features, are prone to failure in rain. According to the report, 69% of tests conducted with simulated rainfall resulted in test vehicles crossing lane markers, and 33% of simulations resulted in collisions at 35 mph. Surprisingly, risk of accidents di... » read more

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Chip Industry Week In Review

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.

by The SE Staff

Chip Industry Week In Review

Onsemi to buy Synaptics; IBM's 7Å chip w/40% more SRAM area; 1nm MoS2 nanotubes; AI pressure points; memory updates; $250M CHIPS Act award; trade secret theft; new advanced packaging site; MEMS capacity; humanoids; earnings.

by The SE Staff

Chip Industry Week In Review

Apple-Intel is on, says Trump; Amkor's big win; Intel 18A-P; Amazon to sell its AI chips; Rambus' automotive RoT; Brewer's buy; VLSI Symposium tech; CHIPS Act funding; MIT sensor; RISC-V CPU fuzzing.

by The SE Staff

Agentic AI Is Changing Data Center Architectures

Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency.

by Ann Mutschler

I/O Design Challenges Grow In AI Data Centers And HPC Clusters

Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnect protocols, requiring design tradeoffs and extra reliability measures.

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The Sub-2nm Paradox

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TSMC Tech Symposium 2026, By The Numbers

Foundry rolls out aggressive new roadmap, focusing on area, power, and latency.

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CPO Is Extending The Limits Of What’s Possible In AI Data Centers

Co-packaged optics technology will have a big impact on system power and the cost of data movement.

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Memory Wall Gets Higher

With SRAM failing to scale in recent process nodes, the industry must assess its impact on all forms of computing. There are no easy solutions on the horizon.

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