Chip Industry Week In Review


IBM unveiled a 7Å transistor architecture that uses staggered nanosheet transistors stacked on a precisely beveled angle, almost like tiles on a roof. That allows more transistors to be crammed into a given area, boosting performance by 50% or power efficiency by up to 70%. Perhaps even more important, IBM claims a 40% improvement in SRAM scaling, which is orders of magnitude faster and lower ... » read more

Week In Review: Manufacturing, Test


Fab tools TEL plans to ship its leading-edge coater/developer system to the joint Imec-ASML research lab, which is working on high-NA extreme ultraviolet (EUV) lithography. The equipment will be integrated with the EXE:5000, ASML’s next-generation high-NA EUV lithography system. The 0.55 numerical aperture (NA) tool is slated to be operational in 2023. Today's EUV is in production, but there... » read more