tag: NVlink

PCIe Benefits From AI, Despite Scaling Protocols
By Ed Sperling - 10 Jun, 2026 - Comments: 0

Key takeaways: PCIe remains a critical technology for non-AI processing. For AI, PCIe will be strengthened by scale-out, agentic AI, and even some scale-up. CXL is seeing uptake, and some even think it could participate in AI processing. PCIe has been the go-to network for most data traffic moving from a processor to devices located elsewhere, which is also what the new data... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Verifying Scale-Up And Scale-Out In Data Centers
By Ed Sperling - 26 Feb, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

CXL Thriving As Memory Link
By Karen Heyman - 16 Sep, 2024 - Comments: 0

CXL is emerging from a jumble of interconnect standards as a predictable way to connect memory to various processing elements, as well as to share memory resources within a data center. Compute Express Link is built on a PCI Express foundation and supported by nearly all the major chip companies. It is used to link CPUs, GPUs, FPGAs, and other purpose-built accelerators using serial communic... » read more

Which Chip Interconnect Protocol Is Better?
By Ed Sperling - 11 May, 2020 - Comments: 0

Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversation... » read more

Conflicting Goals In Data Centers
By Gale Morrison - 06 Apr, 2017 - Comments: 0

Two conflicting goals are emerging inside of data centers—speed at any cost, and the ability to extend hardware well beyond its expected lifetime to amortize that cost. Layered across both of those are concerns about how to move data back and forth more efficiently, how to secure it, and how to best integrate different generations of technology. But these widely different goals have create... » read more

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