The Evolution Of High-Level Synthesis


High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Inferencing At The Edge


Geoff Tate, CEO of Flex Logix, talks about the challenges of power and performance at the edge, why this market is so important from a business and technology standpoint, and what factors need to be balanced. » read more

The Automation Of AI


Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Week In Review: Design, Low Power


Cadence teamed up with nine PCB manufacturing partners on an ecosystem to provide easier access to partners' technology files to improve PCB manufacturability. The program, DesignTrue DFM, allows for automated import of a manufacturer's latest DFM rules as well as rule checking in real time as part of the PCB layout process. The nine initial PCB manufactures supporting the program are: Bay Area... » read more